公开(公告)号：US09373775B2

公开(公告)日：2016-06-21

申请号：US13614212

申请日：2012-09-13

Applicant: Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

IPC: H01L27/20 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more unifoimity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.

Abstract translation: 公开了形成存储单元，磁存储单元结构和磁存储单元结构阵列的方法。 方法的实施例包括图案化前体结构以形成包括至少上部离散特征部分和具有更宽的宽度，长度或两者比较高离散特征部分的下部特征部分的阶梯式结构。 该方法使用沿着第一轴线例如x轴，然后沿着垂直于第一轴线或垂直于第一轴线的第二轴线，例如y轴定向的图案化动作。 因此，即使在低于约三十纳米的尺寸下，图案化动作也可允许在多个形成的相邻电池芯结构之间的更大的均匀性。 还公开了磁存储器结构和存储单元阵列。

公开(公告)号：US20140070342A1

公开(公告)日：2014-03-13

申请号：US13614212

申请日：2012-09-13

Applicant: Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

IPC: H01L43/12 ,  H01L29/82

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more unifoimity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.

Abstract translation: 公开了形成存储单元，磁存储单元结构和磁存储单元结构阵列的方法。 方法的实施例包括图案化前体结构以形成包括至少上部离散特征部分和具有更宽的宽度，长度或两者比较高离散特征部分的下部特征部分的阶梯式结构。 该方法使用沿着第一轴线例如x轴，然后沿着垂直于第一轴线或垂直于第一轴线的第二轴线，例如y轴定向的图案化动作。 因此，即使在低于约三十纳米的尺寸下，图案化动作也可允许在多个形成的相邻电池芯结构之间的更大的均匀性。 还公开了磁存储器结构和存储单元阵列。

公开(公告)号：US20130250661A1

公开(公告)日：2013-09-26

申请号：US13427339

申请日：2012-03-22

Applicant: Gurtej S. Sandhu ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Wayne I. Kinney

IPC: G11C11/16 ,  H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract translation: 公开了包括具有自由区域的单元芯的存储单元。 自由区域表现出影响细胞核心内的磁化取向的应变。 应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。 还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

公开(公告)号：US09007818B2

公开(公告)日：2015-04-14

申请号：US13427339

申请日：2012-03-22

Applicant: Gurtej S. Sandhu ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Wayne I. Kinney

IPC: G11C11/16 ,  H01L43/00 ,  G11C11/15 ,  H01L43/08

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract translation: 公开了包括具有自由区域的单元芯的存储单元。 自由区域表现出影响细胞核心内的磁化取向的应变。 应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。 还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

公开(公告)号：US5345104A

公开(公告)日：1994-09-06

申请号：US089382

申请日：1993-07-08

Applicant: Kirk D. Prall ,  Wayne I. Kinney

Inventor： Kirk D. Prall ,  Wayne I. Kinney

IPC: H01L29/167 ,  H01L29/788 ,  H01L29/68

CPC classification number: H01L29/7885 ,  H01L29/167

Abstract: An improved ETOX-type flash memory cell which requires only a single 5-volt power supply for read, write and erase functions. By substituting antimony or the combination of antimony and arsenic for the usual arsenic drain dopant, drain junction depth is reduced, due to the low diffusivity of antimony during high-temperature cycling. In order to maximize the concentration of antimony in the drain region, which is limited to approximately 3.times.10.sup.19 atoms/cm.sup.3 (due to solid solubility characteristics of antimony at standard silicon process activation temperatures in the 800.degree.-1,000.degree. C. range), an antimony implant concentration of approximately 1.times.10.sup.15 atoms/cm.sup.2 is employed. The resulting shallow junction raises the electric field strength at the cell's drain junction, thus increasing the hot electron generation rate and improving the programming efficiency. The decreased junction depth also acts to improve short channel effects such as punch-through and drain-to-gate capacitive coupling. The addition of a boron halo implant to obtain a traditional doubly diffused drain further enhances programming efficiency.

Abstract translation: 一个改进的ETOX型闪存单元，只需要一个5伏电源进行读，写和擦除功能。 通过将锑或锑和砷的组合替代为通常的砷排出掺杂剂，由于在高温循环期间锑的低扩散率，漏极结深度减小。 为了使漏极区域中的锑浓度最大化，限制在约3×1019原子/ cm3（由于标准硅工艺活性温度在800°-1000℃范围内的锑的固体溶解度特性），锑 使用约1×10 15原子/ cm 2的注入浓度。 所产生的浅结点提高了电池漏极结处的电场强度，从而提高了热电子发生速率，提高了编程效率。 减小的结深也可以改善短沟道效应，例如穿通和漏极 - 栅极电容耦合。 添加硼卤素植入物以获得传统的双扩散漏极进一步提高了编程效率。

公开(公告)号：US5046043A

公开(公告)日：1991-09-03

申请号：US105578

申请日：1987-10-08

Applicant: William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

Inventor： William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

IPC: H01L27/115

CPC classification number: H01L27/11502

Abstract: A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier layer above the surface of the substrate for preventing the materials of the ferroelectric capcacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Abstract translation: 铁电电容器结构被设计用于与半导体衬底上的MOS器件一起制造。 铁电电容器包括在衬底表面上的扩散阻挡层，用于防止铁电电容器的材料污染衬底或MOS器件。 铁电电容器包括底电极，薄膜铁电层和顶电极。 形成层间电介质以覆盖铁电薄膜的部分，并提供用于顶部电极的开口。 铁电存储单元包括场效应晶体管和制造在半导体衬底上的铁电电容器。 在一种配置中，铁电电容器偏离场效应晶体管，而在另一种配置中，铁电电容器基本上高于场效应晶体管，以提供更大的密度。

公开(公告)号：US4532700A

公开(公告)日：1985-08-06

申请号：US604563

申请日：1984-04-27

Applicant: Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

Inventor： Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide having a predetermined thickness.

Abstract translation: 提供了一种用于制造在硅体一侧具有介电隔离的硅区的半导体结构的方法。 这通过在硅体中形成一组掩埋区域和具有使其阳极蚀刻比硅体的剩余部分更慢的特性的一组表面区域来实现。 这两组区域限定了硅体中的阳极蚀刻部分以形成多孔硅区域，这些硅区域被氧化以形成将硅表面区域与硅体的其余部分隔离的隔离结构。 通常在P型硅体中，掩埋和表面区域是通过离子注入形成的N型区域。 使用这些N型区域来控制P型材料暴露于阳极蚀刻溶液和形成多孔硅区域，获得的结构是其中表面单晶硅区域与硅体的其余部分通过 均匀的具有预定厚度的二氧化硅层。

公开(公告)号：US5536672A

公开(公告)日：1996-07-16

申请号：US950795

申请日：1992-09-24

Applicant: William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

Inventor： William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

IPC: H01L27/115 ,  H01L21/70

CPC classification number: H01L27/11502

Abstract: A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier above the surface of the substrate for preventing the materials of the ferroelectric capacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Abstract translation: 铁电电容器结构被设计用于与半导体衬底上的MOS器件一起制造。 铁电电容器包括在衬底表面上方的扩散阻挡层，用于防止铁电电容器的材料污染衬底或MOS器件。 铁电电容器包括底电极，薄膜铁电层和顶电极。 形成层间电介质以覆盖铁电薄膜的部分，并提供用于顶部电极的开口。 铁电存储单元包括场效应晶体管和制造在半导体衬底上的铁电电容器。 在一种配置中，铁电电容器偏离场效应晶体管，而在另一种配置中，铁电电容器基本上高于场效应晶体管，以提供更大的密度。

公开(公告)号：US5357463A

公开(公告)日：1994-10-18

申请号：US977644

申请日：1992-11-17

Applicant: Wayne I. Kinney

Inventor： Wayne I. Kinney

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/40

CPC classification number: G11C16/3459 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3454 ,  G11C2216/28

Abstract: A method of erasing, programming, and verifying a flash electrically erasable programmable read-only memory where all cells are first erased to a high threshold voltage, preferably by simultaneous Fowler-Nordheim tunnelling, and then selected cells are programmed to a low threshold voltage using Fowler-Nordheim tunnelling. Programming is achieved by applying a negative voltage to the selected wordline and applying a positive voltage to the selected bitline. Only those cells which have both the wordline and bitline selected will have sufficient wordline-to-bitline voltage difference to cause programming. A key advantage of this new method is that a verification (read) procedure can be used to monitor for the desirable tight distribution, low threshold voltage V.sub.t on programmed cells and re-program only those cells which have a V.sub.t higher than the desired V.sub.t. The resulting tight distribution of cell current in programmed cells will lead to faster and more reliable read characteristics for these devices.

Abstract translation: 一种擦除，编程和验证闪存电可擦除可编程只读存储器的方法，其中所有单元首先被擦除到高阈值电压，优选地通过同时的Fowler-Nordheim隧道，然后选择的单元被编程为低阈值电压，使用 福勒 - 诺德海隧道。 通过对所选择的字线施加负电压并对所选择的位线施加正电压来实现编程。 只有同时选择了字线和位线的那些单元才能具有足够的字线到位线的电压差来进行编程。 这种新方法的一个关键优点是可以使用验证（读取）程序来监视所需的紧密分配，编程单元上的低阈值电压Vt，并仅重新编程具有高于所需Vt的Vt的那些单元。 编程单元中细胞电流的紧密分布将导致这些器件更快更可靠的读取特性。

公开(公告)号：US5995408A

公开(公告)日：1999-11-30

申请号：US201522

申请日：1998-11-30

Applicant: Wayne I. Kinney

Inventor： Wayne I. Kinney

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A ferroelectric memory device having a folded bit line architecture. The ferroelectric memory device may include a selectable upper even memory cell connected to an upper even bit line, a sense amplifier having a first input and a second input; control circuitry operable to connect an upper odd bit line to a lower odd bit line at the first input of the sense amplifier, to connect the upper even bit line to the second input of the sense amplifier, and to isolate a lower even bit line from the second input of the sense amplifier; and a selectable lower odd reference cell, connected to the lower odd bit line.

Abstract translation: 具有折叠位线架构的铁电存储器件。 铁电存储器件可以包括连接到高位偶数位线的可选择的上部偶极存储器单元，具有第一输入和第二输入的读出放大器; 控制电路可操作以将高位奇数位线连接到读出放大器的第一输入端的低位奇数位线，以将上部偶数位线连接到读出放大器的第二输入端，并将较低的偶数位线与 读出放大器的第二输入; 以及连接到下位奇数位线的可选择的下部奇数参考单元。