A ferroelectric memory device having a folded bit line architecture. The ferroelectric memory device may include a selectable upper even memory cell connected to an upper even bit line, a sense amplifier having a first input and a second input; control circuitry operable to connect an upper odd bit line to a lower odd bit line at the first input of the sense amplifier, to connect the upper even bit line to the second input of the sense amplifier, and to isolate a lower even bit line from the second input of the sense amplifier; and a selectable lower odd reference cell, connected to the lower odd bit line.