公开(公告)号：US10608080B2

公开(公告)日：2020-03-31

申请号：US15819306

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L21/84 ,  H01L27/12

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US10593681B1

公开(公告)日：2020-03-17

申请号：US16106176

申请日：2018-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin

IPC: G11C11/00 ,  H01L27/11 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06

Abstract: A semiconductor device includes a bottom tier including a plurality of first vertical transistors and at least one contact disposed on a first inverter gate. The device further includes a top tier including a plurality of second vertical transistors and a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple.

公开(公告)号：US10199352B2

公开(公告)日：2019-02-05

申请号：US15651990

申请日：2017-07-17

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L25/00

Abstract: Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.

公开(公告)号：US10192888B2

公开(公告)日：2019-01-29

申请号：US15488613

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L21/84 ,  H01L21/285 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/283 ,  H01L23/485

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US10147815B2

公开(公告)日：2018-12-04

申请号：US15463545

申请日：2017-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L23/485 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L23/532 ,  H01L29/417 ,  H01L21/285 ,  H01L29/49 ,  H01L29/40

Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.

公开(公告)号：US20180308768A1

公开(公告)日：2018-10-25

申请号：US16010449

申请日：2018-06-16

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Alexander Reznicek ,  Joshua M. Rubin ,  Junli Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

公开(公告)号：US20180261511A1

公开(公告)日：2018-09-13

申请号：US15980256

申请日：2018-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/417 ,  H01L29/161 ,  H01L27/088 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for forming contacts on a semiconductor device includes depositing conductive material in one or more trenches and over an etch stop layer to a height above the etch stop layer, patterning a resist on the conductive material with shapes over one or more source/drain regions in the one or more trenches, and forming one or more trench lines in the one or more trenches and one or more self-aligned contacts below the shapes, including subtractively etching the conductive material to remove the conductive material from over the etch stop layer and to recess the conductive material into the one or more trenches without the shapes.

公开(公告)号：US09991339B2

公开(公告)日：2018-06-05

申请号：US15364578

申请日：2016-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US09954058B1

公开(公告)日：2018-04-24

申请号：US15620437

申请日：2017-06-12

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Alexander Reznicek ,  Joshua M. Rubin ,  Junli Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.

公开(公告)号：US20170294533A1

公开(公告)日：2017-10-12

申请号：US15135756

申请日：2016-04-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.