公开(公告)号：US20140167111A1

公开(公告)日：2014-06-19

申请号：US13912350

申请日：2013-06-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hokyun AHN ,  Jong-Won Lim ,  Jeong-Jin Kim ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。

公开(公告)号：US10020201B2

公开(公告)日：2018-07-10

申请号：US15093814

申请日：2016-04-08

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chi Hoon Jun ,  Sang Choon Ko ,  Seok-Hwan Moon ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Je Ho Na ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/367 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3205 ,  H01L23/473 ,  H01L23/467

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

公开(公告)号：US09159583B2

公开(公告)日：2015-10-13

申请号：US14310784

申请日：2014-06-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Choon Ko ,  Jae Kyoung Mun ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Chi Hoon Jun ,  Seok-Hwan Moon ,  Woo-Young Jang ,  Jeong-Jin Kim ,  Hyungyu Jang ,  Je Ho Na ,  Eun Soo Nam

IPC: H01L21/33 ,  H01L21/321 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L21/3212 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。

公开(公告)号：US09136347B2

公开(公告)日：2015-09-15

申请号：US14311675

申请日：2014-06-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Rak Park ,  Sang Choon Ko ,  Woojin Chang ,  Jae Kyoung Mun ,  Sung-Bum Bae

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49 ,  H01L29/417 ,  H01L29/778 ,  H01L29/737

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/737 ,  H01L29/778 ,  H01L29/7786

Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.

Abstract translation: 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。

公开(公告)号：US20140184333A1

公开(公告)日：2014-07-03

申请号：US13950895

申请日：2013-07-25

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang-Heung LEE ,  Seong-il Kim ,  Dong Min Kang ,  Jong-Won Lim ,  Chull Won Ju ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H03G3/30

CPC classification number: H03F3/08 ,  H03G1/0047 ,  H03G1/0088 ,  H03G3/02 ,  H03G3/3084 ,  H03G11/02

Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a bust packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a bust packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.

Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否施加固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。

公开(公告)号：US20140167175A1

公开(公告)日：2014-06-19

申请号：US13914713

申请日：2013-06-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong-Il KIM ,  Jong-Won Lim ,  Dong Min Kang ,  Sang-Heung Lee ,  Hyung Sup Yoon ,  Chull Won Ju ,  Byoung-Gue Min ,  Jongmin Lee ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。

公开(公告)号：US20140159050A1

公开(公告)日：2014-06-12

申请号：US13935096

申请日：2013-07-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Seong-ll Kim ,  Sang-Heung Lee ,  Dong Min Kang ,  Chull Won Ju ,  Jae Kyoung Mun

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

Abstract translation: 提供场效应晶体管。 场效应晶体管可以包括衬底上的覆盖层，覆盖层上的源欧姆电极和漏极欧姆电极，堆叠在覆盖层上以覆盖源极和漏极欧姆电极的第一绝缘层和第二绝缘层， 包括脚部和头部的栅格电极，所述脚部分连接到所述源欧姆电极和所述漏极欧姆电极之间的衬底，并且所述头部从所述腿部延伸以覆盖所述源极欧姆电极和所述漏极欧姆电极的顶表面 所述第二绝缘层，在所述第二绝缘层上覆盖所述栅格电极的第一平坦化层和所述第一平坦化层上的第一电极，所述第一电极连接到所述源欧姆电极或所述漏极欧姆电极。

公开(公告)号：US09634112B2

公开(公告)日：2017-04-25

申请号：US14633984

申请日：2015-02-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Seong-Il Kim ,  Sang Heung Lee ,  Dong Min Kang ,  Chull Won Ju ,  Jae Kyoung Mun

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/201 ,  H01L29/205 ,  H01L21/285

CPC classification number: H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

公开(公告)号：US09490214B2

公开(公告)日：2016-11-08

申请号：US14845435

申请日：2015-09-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

公开(公告)号：US09159612B2

公开(公告)日：2015-10-13

申请号：US14021269

申请日：2013-09-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。