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公开(公告)号：US08929731B2
公开(公告)日：2015-01-06
申请号：US13687741
申请日：2012-11-28
Inventor： Chun Ju Youn , Joong-Seon Choe , Jong-Hoi Kim , Duk Jun Kim , Yong-Hwan Kwon , Eun Soo Nam
IPC: H04B10/08 , H04B17/00 , H04B10/06 , H04B10/61 , H04B10/079
CPC classification number: H04B10/614 , H04B10/0799
Abstract: An apparatus for measuring performance of a coherent optical receiver includes a beam splitter splitting light into first and second paths, a first optical modulator modulating the first path light, a variable optical attenuator controlling an optical power of the first optical modulator, a first polarization controller transmitting a signal controlling polarization of an output of the variable optical attenuator to the coherent optical receiver, a second optical modulator modulating the second path light, a variable optical delay line delaying time of an output of the second optical modulator, a second polarization controller transmitting a signal controlling polarization of an output of the variable optical delay line to the coherent optical receiver, a network analyzer measuring performance of the coherent optical receiver and controlling the optical modulators, and a controller transmitting a control signal to the optical modulators.
Abstract translation: 一种用于测量相干光接收机性能的装置，包括将光分成第一和第二路径的光束分配器，调制第一路径光的第一光调制器，控制第一光调制器的光功率的可变光衰减器，第一偏振控制器 将所述可变光衰减器的输出的偏振信号控制到所述相干光接收器，调制所述第二路径光的第二光调制器，所述第二光调制器的输出的可变光延迟线延迟时间，第二偏振控制器发送 控制可变光延迟线到相干光接收机的输出的偏振的信号，测量相干光接收机的性能并控制光调制器的网络分析仪，以及向光调制器发送控制信号的控制器。
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公开(公告)号：US20140184333A1
公开(公告)日：2014-07-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung LEE , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/30
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a bust packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a bust packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否施加固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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公开(公告)号：US20140167175A1
公开(公告)日：2014-06-19
申请号：US13914713
申请日：2013-06-11
Inventor： Seong-Il KIM , Jong-Won Lim , Dong Min Kang , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Byoung-Gue Min , Jongmin Lee , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L27/088 , H01L29/66
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.
Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。
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公开(公告)号：US09905654B2
公开(公告)日：2018-02-27
申请号：US15215414
申请日：2016-07-20
Inventor： Dong Yun Jung , Hyun Soo Lee , Sang Choon Ko , Minki Kim , Jeho Na , Eun Soo Nam , Young Rak Park , Junbo Park , Hyung Seok Lee , Hyun-Gyu Jang , Chi Hoon Jun
IPC: H01L29/205 , H01L29/66 , H01L29/872 , H01L29/20
CPC classification number: H01L29/205 , H01L29/2003 , H01L29/66212 , H01L29/872
Abstract: Provided is a bridge diode according to an embodiment of the inventive concept. The bridge diode includes a first structure including a first lower nitride film and a first upper nitride film, which are laminated on the substrate, a second structure including a second lower nitride film and a second upper nitride film, which are laminated on the substrate, a first electrode structural body disposed on the first structure, and a second electrode structural body disposed on the second structure. The first electrode structural body includes a first electrode, a second electrode, and a third electrode, which are arranged in a clockwise direction, the second electrode structural body includes a fourth electrode, a fifth electrode, and a sixth electrode, which are arranged in a clockwise direction, the first electrode and the sixth electrode, which are connected to each other, are connected to an external circuit, the third electrode and the fourth electrode, which are connected to each other, are connected to an external circuit, and each of the second electrode and the fifth electrode is connected to the external circuit.
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公开(公告)号：US09899226B2
公开(公告)日：2018-02-20
申请号：US14658121
申请日：2015-03-13
Inventor： Ho Kyun Ahn , Hae Cheon Kim , Jong Won Lim , Dong Min Kang , Yong Hwan Kwon , Seong Il Kim , Zin Sig Kim , Eun Soo Nam , Byoung Gue Min , Hyung Sup Yoon , Kyung Ho Lee , Jong Min Lee , Kyu Jun Cho
IPC: H01L29/40 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/51 , H01L29/20 , H01L29/45
CPC classification number: H01L21/28264 , H01L29/2003 , H01L29/407 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
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Patent Agency Ranking
公开(公告)号：US09337121B2
公开(公告)日：2016-05-10
申请号：US14324724
申请日：2014-07-07
Inventor： Chi Hoon Jun , Sang Choon Ko , Seok-Hwan Moon , Woojin Chang , Sung-Bum Bae , Young Rak Park , Je Ho Na , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/367 , H01L21/308 , H01L23/473 , H01L23/467 , H01L21/3065 , H01L21/3205
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。
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公开(公告)号：US09224830B2
公开(公告)日：2015-12-29
申请号：US13914713
申请日：2013-06-11
Inventor： Seong-Il Kim , Jong-Won Lim , Dong Min Kang , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Byoung-Gue Min , Jongmin Lee , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/812 , H01L29/66 , H01L29/40 , H01L29/41 , H01L29/423 , H01L29/778 , H01L29/16 , H01L29/20
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.
Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。
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18.发明授权公开(公告)号：US09031421B2
公开(公告)日：2015-05-12
申请号：US13934589
申请日：2013-07-03
Inventor： Joong-Seon Choe , Chun Ju Youn , Jong-Hoi Kim , Duk Jun Kim , Yong-Hwan Kwon , Kwang-Seong Choi , Eun Soo Nam
IPC: H04B10/06 , H04B10/077
CPC classification number: H04B10/0779
Abstract: Provided is a method of measuring signal transmission time difference of a measuring device. The measuring device according to embodiments, by measuring a skew on two optical paths through signal delays of sufficient sizes for skew measurement on the optical paths, even a skew having a minute size can be measured within a measurable range.
Abstract translation: 提供了测量装置的信号传输时间差的测量方法。 根据实施例的测量装置可以在可测量的范围内测量通过在光路上经过足够尺寸的信号延迟的信号延迟测量两个光路上的偏斜测量，甚至具有微小尺寸的偏斜。
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公开(公告)号：US08941231B2
公开(公告)日：2015-01-27
申请号：US13938324
申请日：2013-07-10
Inventor： Young Rak Park , Sang Choon Ko , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Sung-Bum Bae , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/12 , H01L29/66 , H01L23/522 , H01L23/532 , H01L23/66
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。
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公开(公告)号：US08901608B2
公开(公告)日：2014-12-02
申请号：US13908076
申请日：2013-06-03
Inventor： Jong-Won Lim , Hokyun Ahn , Woojin Chang , Dong Min Kang , Seong-Il Kim , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L33/00 , H01L29/66 , H01L29/778
CPC classification number: H01L29/778 , H01L29/402 , H01L29/42316 , H01L29/66431
Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.
Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。
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