公开(公告)号：US20180358222A1

公开(公告)日：2018-12-13

申请号：US15979842

申请日：2018-05-15

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Samuel E. GOTTHEIM ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOZHIZAWA ,  Abhijit Basu MALLICK ,  Srinivas GANDIKOTA

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/683 ,  H01J37/32 ,  C23C16/27 ,  C23C16/505 ,  C23C16/56 ,  G03F7/20

CPC classification number: H01L21/02115 ,  C23C16/272 ,  C23C16/505 ,  C23C16/56 ,  G03F7/70033 ,  H01J37/32082 ,  H01J37/32715 ,  H01J2237/3321 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/6831 ,  H01L27/11551 ,  H01L27/11578

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high-density films for patterning applications. In one implementation, a method of processing a substrate is provided. The method includes flowing a hydrocarbon-containing gas mixture into a processing volume of a process chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.5 mTorr and about 10 Torr. The method further includes generating a plasma at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a diamond-like carbon film on the substrate. The diamond-like carbon film has a density greater than 1.8 g/cc and a stress less than −500 MPa.

公开(公告)号：US20180294157A1

公开(公告)日：2018-10-11

申请号：US15925976

申请日：2018-03-20

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Abhijit Basu MALLICK ,  Yihong CHEN

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/027 ,  C23C16/24 ,  C23C16/50 ,  C23C16/56

CPC classification number: H01L21/0337 ,  C23C16/24 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67017 ,  H01L21/67103 ,  H01L21/67248

Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.

公开(公告)号：US20180286674A1

公开(公告)日：2018-10-04

申请号：US15936751

申请日：2018-03-27

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Rui CHENG ,  Abhijit Basu MALLICK

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02592 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0649

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20170372953A1

公开(公告)日：2017-12-28

申请号：US15633366

申请日：2017-06-26

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha ROY ,  Kelvin CHAN ,  Hien Minh LE ,  Sanjay KAMATH ,  Abhijit Basu MALLICK ,  Srinivas GANDIKOTA ,  Karthik JANAKIRAMAN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L21/28506 ,  C23C16/0272 ,  C23C16/06 ,  C23C16/402 ,  C23C16/505 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02697 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76876 ,  H01L27/11582

Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

公开(公告)号：US20170352586A1

公开(公告)日：2017-12-07

申请号：US15175880

申请日：2016-06-07

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Susmit Singha ROY ,  Pramit MANNA ,  Abhijit Basu MALLICK

IPC: H01L21/768 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11524 ,  H01L23/528 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.

公开(公告)号：US20170207088A1

公开(公告)日：2017-07-20

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20170125239A1

公开(公告)日：2017-05-04

申请号：US15364125

申请日：2016-11-29

Applicant: Applied Materials, Inc.

Inventor： Yihong CHEN ,  Kelvin CHAN ,  Shaunak MUKHERJEE ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/45525 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/53228

Abstract: Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the substrate having terminal hydroxyl groups. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma and H2O soak in order to perform an additional silylation. Further methods include catalyzing the exposed surfaces using a Lewis acid, directionally inactivating the exposed first and second surfaces and deposition of a silicon containing layer on the sidewall surfaces. Multiple plasma treatments may be performed to deposit a layer having a desired thickness.

公开(公告)号：US20160314960A1

公开(公告)日：2016-10-27

申请号：US15094512

申请日：2016-04-08

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Pramit MANNA ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L21/0234 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/3105 ,  H01L21/32

Abstract: The present disclosure relates to methods for improving adhesion between a hardmask layer and a subsequent layer on the hardmask layer. Particularly, embodiment of the present disclosure relates to methods for improving adhesion between a metal-doped amorphous carbon layer and a mask layer, such as a silicon oxide layer, a silicon nitride layer, or an amorphous silicon layer. One embodiment of the present disclosure includes performing a plasma treatment to the metal-doped amorphous carbon layer.

Abstract translation: 本公开涉及用于改善硬掩模层和硬掩模层上的后续层之间的粘合性的方法。 特别地，本公开的实施方案涉及用于改善金属掺杂非晶碳层和掩模层之间的粘附性的方法，例如氧化硅层，氮化硅层或非晶硅层。 本公开的一个实施方案包括对金属掺杂的无定形碳层进行等离子体处理。

公开(公告)号：US20160017495A1

公开(公告)日：2016-01-21

申请号：US14799799

申请日：2015-07-15

Applicant: Applied Materials, Inc.

Inventor： Yihong CHEN ,  Kelvin CHAN ,  Martin Jay SEAMONS ,  Shaunak MUKHERJEE ,  Abhijit Basu MALLICK ,  Jianhua ZHOU ,  Kang Sub YIM

IPC: C23C16/505

CPC classification number: C23C16/505 ,  C23C16/325 ,  C23C16/4404 ,  C23C16/455 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274

Abstract: Embodiments disclosed herein generally include methods for forming porous low k dielectric films. In one embodiment, a method of forming a porous low k dielectric film on a substrate using PECVD and in situ radical curing in a processing chamber is disclosed. The method includes introducing radicals into a processing region of the processing chamber, introducing a gas mixture into the processing region of the processing chamber, forming a plasma in the processing region and depositing the porous low k dielectric film on the substrate.

Abstract translation: 本文公开的实施方案通常包括形成多孔低k电介质膜的方法。 在一个实施例中，公开了一种使用PECVD在基板上形成多孔低k电介质膜并在处理室中进行原位自由基固化的方法。 该方法包括将自由基引入处理室的处理区域，将气体混合物引入处理室的处理区域，在处理区域中形成等离子体，并在基板上沉积多孔低k电介质膜。

公开(公告)号：US20140231384A1

公开(公告)日：2014-08-21

申请号：US14177893

申请日：2014-02-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Brian Saxton UNDERWOOD ,  Abhijit Basu MALLICK ,  Nitin INGLE ,  Roman GOUK ,  Steven VERHAVERBEKE

IPC: G11B5/85

CPC classification number: G11B5/85 ,  G11B5/855

Abstract: Method and apparatus for forming a patterned magnetic substrate are provided. A patterned resist is formed on a magnetically active surface of a substrate. An oxide layer is formed over the patterned resist by a flowable CVD process. The oxide layer is etched to expose portions of the patterned resist. The patterned resist is then etched, using the etched oxide layer as a mask, to expose portions of the magnetically active surface. A magnetic property of the exposed portions of the magnetically active surface is then modified by directing energy through the etched resist layer and the etched oxide layer, which are subsequently removed from the substrate.

Abstract translation: 提供了用于形成图案化磁性基底的方法和装置。 在基板的磁性活性表面上形成图案化的抗蚀剂。 通过可流动的CVD工艺在图案化的抗蚀剂上形成氧化物层。 蚀刻氧化物层以暴露图案化抗蚀剂的部分。 然后使用蚀刻的氧化物层作为掩模蚀刻图案化的抗蚀剂，以暴露磁性活性表面的部分。 然后通过将能量引导通过经蚀刻的抗蚀剂层和经蚀刻的氧化物层（随后从衬底去除）来改变磁性活性表面的暴露部分的磁性。