公开(公告)号：US20210043449A1

公开(公告)日：2021-02-11

申请号：US17045453

申请日：2019-04-08

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOSHIZAWA ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  C23C16/26 ,  H01L21/033

Abstract: Embodiments herein provide methods of depositing an amorphous carbon layer using a plasma enhanced chemical vapor deposition (PECVD) process and hard masks formed therefrom. In one embodiment, a method of processing a substrate includes positioning a substrate on a substrate support, the substrate support disposed in a processing volume of a processing chamber, flowing a processing gas comprising a hydrocarbon gas and a diluent gas into the processing volume, maintaining the processing volume at a processing pressure less than about 100 mTorr, igniting and maintaining a deposition plasma of the processing gas by applying a first power to one of one or more power electrodes of the processing chamber, maintaining the substrate support at a processing temperature less than about 350° C., exposing a surface of the substrate to the deposition plasma, and depositing an amorphous carbon layer on the surface of the substrate.

公开(公告)号：US20200051815A1

公开(公告)日：2020-02-13

申请号：US16659194

申请日：2019-10-21

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Rui CHENG ,  Abhijit Basu MALLICK

IPC: H01L21/02

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20190221422A1

公开(公告)日：2019-07-18

申请号：US16246776

申请日：2019-01-14

Applicant: Applied Materials, Inc.

Inventor： Fei WANG ,  Miaojun WANG ,  Pramit MANNA ,  Shishi JIANG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/027

Abstract: Methods of selectively depositing a mask layer on a surface of a patterned substrate and self-aligned patterned masks are provided herein. In one embodiment, a method of selectivity depositing a mask layer includes positioning the patterned substrate on a substrate support in a processing volume of a processing chamber, exposing the surface of the patterned substrate to a parylene monomer gas, forming a first layer on the patterned substrate, wherein the first layer comprises a patterned parylene layer, and depositing a second layer on the first layer. In another embodiment, a self-aligned patterned mask comprises a parylene layer comprising a plurality of parylene features and a plurality of openings, the parylene layer is disposed on a patterned substrate comprising a dielectric layer and a plurality of metal features, the plurality of metal feature comprise a parylene deposition inhibitor metal, and the plurality of parylene features are selectivity formed on dielectric surfaces of the dielectric layer.

公开(公告)号：US20190189435A1

公开(公告)日：2019-06-20

申请号：US16201095

申请日：2018-11-27

Applicant: Applied Materials, Inc.

Inventor： Shishi JIANG ,  Kurtis LESCHKIES ,  Pramit MANNA ,  Abhijit Basu MALLICK ,  Steven VERHAVERBEKE

IPC: H01L21/02 ,  C23C8/10

Abstract: Implementations described herein generally relate to methods for forming a low-k dielectric material on a semiconductor substrate. More specifically, implementations described herein relate to methods of forming a silicon oxide film at high pressure and low temperatures. In one implementation, a method of forming a silicon oxide film is provided. The method comprises loading a substrate having a silicon-containing film formed thereon into a processing region of a high-pressure vessel. The method further comprises forming a silicon oxide film on the silicon-containing film. Forming the silicon oxide film on the silicon-containing film comprises exposing the silicon-containing film to a processing gas comprising steam at a pressure greater than about 1 bar and maintaining the high-pressure vessel at a temperature between about 100 degrees Celsius and about 500 degrees Celsius.

公开(公告)号：US20190019724A1

公开(公告)日：2019-01-17

申请号：US15991376

申请日：2018-05-29

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Yi YANG ,  Abhijit Basu MALLICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3215

Abstract: Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.

公开(公告)号：US20180080125A1

公开(公告)日：2018-03-22

申请号：US15822551

申请日：2017-11-27

Applicant: Applied Materials, Inc.

Inventor： Jianhua ZHOU ,  Juan Carlos ROCHA-ALVAREZ ,  Yihong CHEN ,  Abhijit Basu MALLICK ,  Oscar LOPEZ ,  Ningli LIU

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/458 ,  C23C16/509

CPC classification number: C23C16/45565 ,  C23C16/45574 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/5096 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32449

Abstract: Embodiments disclosed herein generally include an apparatus for radical-based deposition of dielectric films. The apparatus includes a processing chamber, a radical source coupled to the processing chamber, a substrate support disposed in the processing chamber, and a dual-channel showerhead disposed between the radical source and the substrate support. The dual-channel showerhead includes a plurality of tubes and an internal volume surrounding the plurality of tubes. The plurality of tubes and the internal volume are surrounded by one or more annular channels embedded in the dual-channel showerhead. The dual-channel showerhead further includes a first inlet connected to the one or more channels and a second inlet connected to the internal volume. The processing chamber may be a PECVD chamber, and the apparatus is capable of performing a cyclic process (alternating radical based CVD and PECVD).

公开(公告)号：US20160336174A1

公开(公告)日：2016-11-17

申请号：US15112737

申请日：2015-01-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Brian Saxton UNDERWOOD ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  C23C16/505 ,  C23C16/40 ,  H01J37/32 ,  C23C16/452

Abstract: A silicon and oxygen-containing film, such as a silicon dioxide film, is deposited in the absence of an oxidizer by introducing siloxane precursors into a plasma processing chamber and dissociating at least some of the Si—H bonds of the siloxane precursors by, for example, exposing the siloxane precursors to a low energy plasma. The silicon and oxygen-containing film may be formed on an oxidation-prone surface without oxidizing the oxidation-prone surface. The deposited silicon and oxygen-containing film may serve as an initiation layer for a silicon dioxide bulk layer that is formed on top of the initiation layer using conventional silicon oxide deposition techniques, such as exposing the siloxane precursors to an oxygen-containing plasma. The initiation layer may be post-treated or cured to reduce the concentration of Si—H bonds prior to or after the deposition of the bulk layer.

Abstract translation: 通过将硅氧烷前体引入等离子体处理室中并将硅氧烷前体的至少一些Si-H键解离，通过在不存在氧化剂的情况下沉积硅和含氧膜，例如二氧化硅膜， 例如，将硅氧烷前体暴露于低能量等离子体。 可以在氧化容易发生的表面上形成硅和含氧膜，而不氧化易氧化的表面。 沉积的硅和含氧膜可以用作二氧化硅体层的起始层，其使用常规的氧化硅沉积技术形成在起始层的顶部，例如将硅氧烷前体暴露于含氧等离子体。 可以对引发层进行后处理或固化，以在堆积层沉积之前或之后降低Si-H键的浓度。

公开(公告)号：US20160027614A1

公开(公告)日：2016-01-28

申请号：US14697385

申请日：2015-04-27

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Abhijit Basu MALLICK ,  Mukund SRINIVASAN ,  Rui CHENG

IPC: H01J37/32 ,  C23C16/06 ,  C23C16/26 ,  C23C16/04

CPC classification number: C23C16/26 ,  C23C16/042 ,  C23C16/06 ,  C23C16/30 ,  H01J37/32091

Abstract: Embodiments of the present disclosure relate to a metal-doped amorphous carbon hardmask for etching the underlying layer, layer stack, or structure. In one embodiment, a method of processing a substrate in a processing chamber includes exposing a substrate to a gas mixture comprising a carbon-containing precursor and a metal-containing precursor, reacting the carbon-containing precursor and the metal-containing precursor in the processing chamber to form a metal-doped carbon layer over a surface of the substrate, forming in the metal-doped carbon layer a defined pattern of through openings, and transferring the defined pattern to an underlying layer beneath the metal-doped carbon layer using the metal-doped carbon layer as a mask. An etch hardmask using the inventive metal-doped amorphous carbon film provides reduced compressive stress, high hardness, and therefore higher etch selectivity.

Abstract translation: 本公开的实施例涉及用于蚀刻下层，层叠或结构的金属掺杂非晶碳硬掩模。 在一个实施方案中，在处理室中处理衬底的方法包括将衬底暴露于包含含碳前体和含金属的前体的气体混合物中，使该含碳前体和含金属的前体在加工过程中反应 室，以在衬底的表面上形成金属掺杂碳层，在金属掺杂碳层中形成限定图形的通孔，并将定义的图案转移到金属掺杂碳层下方的下层，使用金属 掺杂碳层作为掩模。 使用本发明的金属掺杂的非晶碳膜的蚀刻硬掩模提供降低的压缩应力，高硬度，因此提高了蚀刻选择性。

公开(公告)号：US20240339316A1

公开(公告)日：2024-10-10

申请号：US18746799

申请日：2024-06-18

Applicant: Applied Materials, Inc.

Inventor： Aykut AYDIN ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Abhijit Basu MALLICK ,  Takehito KOSHIZAWA ,  Bo QI

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02211 ,  H01L21/02271

Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

公开(公告)号：US20220310448A1

公开(公告)日：2022-09-29

申请号：US17839170

申请日：2022-06-13

Applicant: Applied Materials, Inc.

Inventor： Xin LIU ,  Fei WANG ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/768 ,  C23C16/01 ,  C23C16/24 ,  C23C16/455 ,  C23C16/46 ,  C23C16/56 ,  H01L21/02 ,  H01L21/3205

Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.