公开(公告)号：US20080132068A1

公开(公告)日：2008-06-05

申请号：US11633929

申请日：2006-12-05

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: H01L21/44

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract translation: 制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二 导电体在开口处。

公开(公告)号：US09343666B2

公开(公告)日：2016-05-17

申请号：US13529284

申请日：2012-06-21

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael Vanbuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffery A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael Vanbuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffery A. Shields

IPC: H01L21/20 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract translation: 制造存储器件的现有方法包括以下步骤：提供电介质层，在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US20090109598A1

公开(公告)日：2009-04-30

申请号：US11980213

申请日：2007-10-30

Applicant: Steven Avanzino ,  Tzu-Ning Fang ,  Swaroop Kaza ,  Dongxiang Liao ,  Wai Lo ,  Christie Marrian ,  Sameer Haddad

Inventor： Steven Avanzino ,  Tzu-Ning Fang ,  Swaroop Kaza ,  Dongxiang Liao ,  Wai Lo ,  Christie Marrian ,  Sameer Haddad

IPC: H01G4/002 ,  H01G7/00

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G13/00 ,  H01L27/101 ,  H01L28/57 ,  Y10T29/435

Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

Abstract translation: 在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，首先提供第一电极。 在第一电极上设置氧化物层，在氧化物层上设置保护层。 提供通过保护层的开口以暴露氧化物层的一部分，氧化层的暴露部分下方的第一电极的一部分被氧化。 提供与氧化物层的暴露部分接触的第二电极。 在替代实施例中，可以消除初始提供的氧化物层，并且可以在开口中提供绝缘材料的间隔物。

公开(公告)号：US20060145134A1

公开(公告)日：2006-07-06

申请号：US11335329

申请日：2006-01-19

Applicant: Mark Hart ,  Christie Marrian ,  Gary McClelland ,  Charles Rettner ,  Hemantha Wickramasinghe

Inventor： Mark Hart ,  Christie Marrian ,  Gary McClelland ,  Charles Rettner ,  Hemantha Wickramasinghe

IPC: H01L29/04

CPC classification number: H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

公开(公告)号：US08089113B2

公开(公告)日：2012-01-03

申请号：US11633929

申请日：2006-12-05

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: H01L29/94 ,  H01L27/108

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract translation: 制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二 导电体在开口处。

公开(公告)号：US07916529B2

公开(公告)日：2011-03-29

申请号：US12370932

申请日：2009-02-13

Applicant: Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

Inventor： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

IPC: G11C11/36

CPC classification number: H01L27/1021 ,  G11C5/04 ,  G11C11/36 ,  H01L27/24 ,  H01L29/868

Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

Abstract translation: 提供采用一个或多个半导体PIN二极管的存储架构。 存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

公开(公告)号：US20100208517A1

公开(公告)日：2010-08-19

申请号：US12370932

申请日：2009-02-13

Applicant: Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

Inventor： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

IPC: G11C11/36 ,  H01L29/868 ,  H01L21/425 ,  G11C7/00

CPC classification number: H01L27/1021 ,  G11C5/04 ,  G11C11/36 ,  H01L27/24 ,  H01L29/868

Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

Abstract translation: 提供采用一个或多个半导体PIN二极管的存储架构。 存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

公开(公告)号：US20050265072A1

公开(公告)日：2005-12-01

申请号：US10856547

申请日：2004-05-28

Applicant: Mark Hart ,  Chung Lam ,  Christie Marrian ,  Gary McClelland ,  Simone Raoux ,  Charles Rettner ,  Hemantha Wickramasinghe

Inventor： Mark Hart ,  Chung Lam ,  Christie Marrian ,  Gary McClelland ,  Simone Raoux ,  Charles Rettner ,  Hemantha Wickramasinghe

IPC: G11C11/00 ,  G11C16/02 ,  H01L27/24

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/72 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1666

Abstract: A method and structure for a memory cell comprising a phase change material; a heating element in thermal contact with the phase change material, wherein the heating element is adapted to induce a phase change in the phase change material; and electrical lines configured to pass current through the heating element, wherein the phase change material and the heating element are arranged in a configuration other than being electrically connected in series. The memory cell further comprises a sensing element in thermal contact with the phase change material, wherein the sensing element is adapted to detect a change in at least one physical property of the phase change material, wherein the sensing element is adapted to detect a change in a thermal conductivity of the phase change material.

Abstract translation: 一种包括相变材料的存储单元的方法和结构; 与所述相变材料热接触的加热元件，其中所述加热元件适于引起所述相变材料的相变; 以及配置为使电流通过所述加热元件的电线，其中所述相变材料和所述加热元件被布置成不是串联电连接的构造。 存储单元还包括与相变材料热接触的感测元件，其中感测元件适于检测相变材料的至少一个物理特性的变化，其中感测元件适于检测相变材料的变化 相变材料的导热性。

公开(公告)号：US20050242338A1

公开(公告)日：2005-11-03

申请号：US10835814

申请日：2004-04-30

Applicant: Mark Hart ,  Christie Marrian ,  Gary McClelland ,  Charles Rettner ,  Hemantha Wickramasinghe

Inventor： Mark Hart ,  Christie Marrian ,  Gary McClelland ,  Charles Rettner ,  Hemantha Wickramasinghe

IPC: H01L21/20 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract translation: 用于制造的方法和自对准（交叉点）存储器件的结构包括在第一方向和第二方向上的线（线）。 使用硬掩模材料形成第一方向上的导线，该硬掩模材料抵抗用于在第一和第二方向上产生线的预选蚀刻工艺。 因此，用于沿第一方向的线的硬掩模材料形成存储器堆叠的一部分。

公开(公告)号：US5703373A

公开(公告)日：1997-12-30

申请号：US552651

申请日：1995-11-03

Applicant: Martin C. Peckerar ,  Christie Marrian

Inventor： Martin C. Peckerar ,  Christie Marrian

IPC: H01J37/244 ,  H01J37/30

CPC classification number: H01J37/244 ,  H01J2237/2441 ,  H01J2237/30438

Abstract: The present invention is a fiducial electron beam detector including an etron beam absorber layer having one or more apertures for transmitting an electron beam, and a conductive or semiconductive structure adapted to produce a current in response to an incident electron beam transmitted through an aperture. When electrons from the electron beam strike this structure, a flow of electrons is created which may be monitored using any of the known methods for detecting current flow. The present invention is also a fiducial electron beam detector including a first semiconductor layer for electron collection, a first responsive layer of essentially parallel lines of conductive material oriented in one direction, where these conductive lines are separated by nonconductive material, and each of the lines is adapted for producing a current responsive to an electron beam, a second semiconductor layer adapted for electron collection, and a second responsive layer of essentially parallel lines of conductive material oriented in another direction, where these conductive lines are separated by nonconductive material, and each of the fines is adapted for producing a current responsive to an electron beam. Diode layers separate each of the semiconductor and responsive layers, to restrict current flow to a single direction. The present invention is also a method for monitoring the position of an electron beam on a film, in an area wherein the beam can create a useful image on the film.

Abstract translation: 本发明是一种基准电子束检测器，其包括具有一个或多个用于透射电子束的孔的电子束吸收层，以及适于响应于通过孔传输的入射电子束而产生电流的导电或半导体结构。 当来自电子束的电子撞击该结构时，产生电子流，其可以使用用于检测电流的任何已知方法进行监测。 本发明还是一种基准电子束检测器，其包括用于电子收集的第一半导体层，在一个方向上定向的基本平行的导电材料线的第一响应层，其中这些导线由非导电材料分开，并且每条线 适于产生响应于电子束的电流，适于电子收集的第二半导体层，以及在另一个方向上定向的基本上平行的导电材料线的第二响应层，其中这些导电线被非导电材料分开，并且每个 的细粉被适于产生响应于电子束的电流。 二极管层分离每个半导体层和响应层，以限制电流流向单个方向。 本发明还是一种用于监测电子束在膜上的位置的方法，其中光束可以在膜上产生有用的图像。