公开(公告)号：US10748904B2

公开(公告)日：2020-08-18

申请号：US16775808

申请日：2020-01-29

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00 ,  H01L27/108 ,  H01L29/10 ,  H01L29/08 ,  H01L27/102 ,  G11C11/4099 ,  G11C11/39 ,  H01L23/528 ,  H01L29/788 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/404 ,  H01L29/78 ,  H01L29/66 ,  H01L29/772 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/403 ,  G11C11/04 ,  G11C11/402

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US10461083B2

公开(公告)日：2019-10-29

申请号：US16106643

申请日：2018-08-21

申请人： Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： H01L27/108 ,  H01L29/788 ,  H01L27/1157 ,  H01L29/78 ,  G11C16/00 ,  G11C16/04 ,  H01L29/06 ,  G11C11/404 ,  G11C11/407

摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

公开(公告)号：US10453847B2

公开(公告)日：2019-10-22

申请号：US16404964

申请日：2019-05-07

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00 ,  H01L27/108 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/22 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/102 ,  G11C11/39 ,  H01L23/528 ,  H01L29/788 ,  H01L29/772 ,  G11C11/4099 ,  G11C11/402 ,  G11C11/04

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US10373685B2

公开(公告)日：2019-08-06

申请号：US16013646

申请日：2018-06-20

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： G11C15/04 ,  H01L27/108 ,  G11C11/404 ,  G11C16/04

摘要： A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

公开(公告)号：US10354718B2

公开(公告)日：2019-07-16

申请号：US16189806

申请日：2018-11-13

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S. Louie ,  Yuniarto Widjaja

IPC分类号： G11C7/02 ,  G11C11/417 ,  G11C5/14 ,  G11C11/412

摘要： Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

公开(公告)号：USRE47381E1

公开(公告)日：2019-05-07

申请号：US15055416

申请日：2016-02-26

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： H04W4/02 ,  H04W4/30 ,  H04W8/00 ,  G06Q30/02 ,  H04L12/58 ,  H04L29/08 ,  H04W40/02 ,  H04W40/24 ,  H04W84/18 ,  H04W4/04

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region and having the first conductivity type; and a gate positioned between the first and second regions and above the top surface; wherein a state of the body region is maintained by applying a voltage to the substrate and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US10204684B2

公开(公告)日：2019-02-12

申请号：US16003350

申请日：2018-06-08

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  H01L29/423 ,  G11C16/06 ,  H01L29/78 ,  H01L27/108 ,  G11C11/56 ,  G11C11/404 ,  H01L29/788 ,  H01L29/49 ,  H01L29/06 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/66 ,  G11C16/04

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

公开(公告)号：US10182845B2

公开(公告)日：2019-01-22

申请号：US14807080

申请日：2015-07-23

申请人： William P. Grant

发明人： William P. Grant

IPC分类号： A61B17/88 ,  A61B17/68 ,  A61B17/80 ,  A61B17/86

摘要： A bone securement apparatus includes a bone plate configured and dimensioned to be applied across a joint of at least two bones or a space between at least two bone fragments. The bone plate includes first and second openings. A beaming member is configured to pass through the first opening, and the beaming member includes a third opening. A support member is configured to pass through the second opening and the third opening.

公开(公告)号：US10028773B2

公开(公告)日：2018-07-24

申请号：US14876149

申请日：2015-10-06

申请人： SpineCraft, LLC

发明人： Kamal Ibrahim ,  Wagdy W. Asaad ,  Thibaut Guffroy

IPC分类号： A61B17/70 ,  A61B90/00 ,  A61B17/86 ,  A61B17/88 ,  A61B17/68 ,  A61B17/56

CPC分类号： A61B17/7079 ,  A61B17/70 ,  A61B17/7002 ,  A61B17/7032 ,  A61B17/7034 ,  A61B17/7035 ,  A61B17/7037 ,  A61B17/7038 ,  A61B17/7049 ,  A61B17/708 ,  A61B17/7085 ,  A61B17/7091 ,  A61B17/8605 ,  A61B17/88 ,  A61B90/03 ,  A61B2017/564 ,  A61B2017/681 ,  A61B2090/037

摘要： Systems, assemblies, components and methods for correcting alignment of one or more vertebrae of a spine are provided. A first elongate derotator member includes a first elongate element having a first proximal end portion and a first distal end portion. The first distal end portion is releasably engageable with a first implant implanted in one of the vertebrae. A second elongate derotator member comprising a second elongate element is releasably engageable with a second implant implanted in the same vertebra. A transverse member is engageable with the first and second elongate elements. A first channel extends axially through the first elongate element and a second channel extends axially through the second elongate element such that a proximal end portion of the first implant can be accessed from a proximal end portion of the first elongate element by inserting a tool through the first channel and a proximal end portion of the second implant can be accessed from a proximal end portion of the second elongate element by inserting the tool or another tool through the second channel.

公开(公告)号：US09922711B2

公开(公告)日：2018-03-20

申请号：US15499519

申请日：2017-04-27

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C11/00 ,  G11C14/00 ,  G11C13/00 ,  H01L27/108 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C14/0045 ,  G11C11/21 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4072 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0027 ,  G11C14/0036 ,  G11C14/009 ,  G11C2013/0073 ,  H01L27/10802 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.