公开(公告)号：US20180240890A1

公开(公告)日：2018-08-23

申请号：US15962023

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/765 ,  H01L21/762 ,  H01L27/02

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

公开(公告)号：US10043826B1

公开(公告)日：2018-08-07

申请号：US15660288

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L29/423 ,  H01L27/12 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/683 ,  H01L21/02 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a first non-insulative region disposed above the substrate, and a second non-insulative region disposed above the first non-insulative region, wherein the first and second non-insulative regions have the same doping type and different doping concentrations. In certain aspects, the semiconductor device also includes a first dielectric layer, a channel region, the first dielectric layer being disposed adjacent to a first side of the channel region, a second dielectric layer disposed adjacent to a second side of the channel region, and a third non-insulative region disposed above the second dielectric layer. In certain aspects, the semiconductor device also includes a fourth non-insulative region disposed adjacent to a third side of the channel region, and a fifth non-insulative region disposed adjacent to a fourth side of the channel region.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US09601607B2

公开(公告)日：2017-03-21

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H03K17/687 ,  H01L29/739 ,  G05F3/16 ,  H01L27/07

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

公开(公告)号：US09496254B2

公开(公告)日：2016-11-15

申请号：US14690144

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L23/52 ,  H01L27/06 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20160218211A1

公开(公告)日：2016-07-28

申请号：US14604544

申请日：2015-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Xia Li ,  Bin Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

Abstract translation: 在特定实施例中，一种装置包括电子隧道结构。 电子隧道结构包括隧道层，沟道层，源极层和漏极层。 隧道层和沟道层位于源极层和漏极层之间。 晶体管器件还包括与电子隧道结构相邻的高k电介质层。

公开(公告)号：US09269492B2

公开(公告)日：2016-02-23

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Pr Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/38 ,  H01G4/005 ,  H01L49/02 ,  H01G4/33 ,  H01G4/10

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20160020220A1

公开(公告)日：2016-01-21

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract translation: 一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。 氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。 金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

公开(公告)号：US20150098270A1

公开(公告)日：2015-04-09

申请号：US14570577

申请日：2014-12-15

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C17/18 ,  G11C11/40

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

Abstract translation: 一种装置包括半导体晶体管结构。 半导体晶体管结构包括电介质材料，沟道区，栅极，源极重叠区域和漏极重叠区域。 源重叠区域是可偏置的，以使源重叠区域和栅极之间的第一电压差超过电介质材料的击穿电压。 漏极重叠区域是可偏置的，以使漏极重叠区域和栅极之间的第二电压差超过击穿电压。 该装置包括耦合到半导体晶体管的本体的阱线。 该装置包括被配置为向阱管线施加电压以防止沟道区域和栅极之间的击穿状态的电路。

公开(公告)号：US20140231957A1

公开(公告)日：2014-08-21

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  PR Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L23/538 ,  H01L27/08

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上互连层的至少一部分的第一电容器板和具有MIM电容层的至少一部分的第二电容器板。