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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    101.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20130026543A1

    公开(公告)日：2013-01-31

    申请号：US13191430

    申请日：2011-07-26

    Applicant: Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

    Inventor： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

    IPC: H01L21/268 ,  H01L29/772

    CPC classification number: H01L21/268 ,  H01L21/26586

    Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

    Abstract translation: 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括：通过在第一扫描方向上单独地发射第一激光，对半导体衬底进行第一退火处理，并且通过在第二扫描方向上单独地发射第二激光，对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有入射角。

    HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION
    102.
    发明申请
    HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION 有权
    高性能HKMG堆栈进行第一次整合

    公开(公告)号：US20130020656A1

    公开(公告)日：2013-01-24

    申请号：US13185112

    申请日：2011-07-18

    Applicant: Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    Inventor： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

    IPC: H01L29/772 ,  H01L21/336

    CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

    Abstract: Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

    Abstract translation: 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

    Transistor, Method for Manufacturing Transistor, and Semiconductor Chip Comprising the Transistor
    103.
    发明申请
    Transistor, Method for Manufacturing Transistor, and Semiconductor Chip Comprising the Transistor 有权
    晶体管，制造晶体管的方法以及包含晶体管的半导体芯片

    公开(公告)号：US20130009217A1

    公开(公告)日：2013-01-10

    申请号：US13378997

    申请日：2011-08-09

    Applicant: Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

    Inventor： Haizhou Yin ,  Jun Luo ,  Huilong Zhu ,  Zhijiong Luo

    IPC: H01L29/772 ,  H01L21/336

    CPC classification number: H01L29/7833 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659

    Abstract: It is provided a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. A method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously. As such, the risk of transistor failure due to atoms or ions of Ni entering the channel region through the source/drain extension regions is reduced.

    Abstract translation: 提供晶体管，晶体管的制造方法和包括晶体管的半导体芯片。 一种用于制造晶体管的方法可以包括：在半导体衬底上限定有源区，以及在有源区上形成栅极堆叠，初级间隔物和源极/漏极区，其中主要间隔物包围栅极堆叠，源极 /漏极区域嵌入有源区域并与主间隔物的相对侧自对准; 形成围绕所述初级间隔物的半导体衬垫，并且在所述栅极叠层的宽度方向上切断所述半导体衬垫的端部，以将所述源极/漏极区彼此隔离; 并且用金属或合金层覆盖源极/漏极区域和半导体衬垫的表面，并对所得结构进行退火，使得在源极/漏极区域的表面上形成金属硅化物，并且使得半导体 间隔物同时转化成硅化物间隔物。 因此，由于通过源极/漏极延伸区域进入沟道区域的Ni的原子或离子导致的晶体管故障的风险降低。

    LARGE DIMENSION DEVICE AND METHOD OF MANUFACTURING SAME IN GATE LAST PROCESS
    104.
    发明申请
    LARGE DIMENSION DEVICE AND METHOD OF MANUFACTURING SAME IN GATE LAST PROCESS 有权
    大尺寸装置及其在门过程中的制造方法

    公开(公告)号：US20120319180A1

    公开(公告)日：2012-12-20

    申请号：US13162453

    申请日：2011-06-16

    Applicant: Harry-Hak-Lay Chuang ,  Ming Zhu

    Inventor： Harry-Hak-Lay Chuang ,  Ming Zhu

    IPC: H01L29/772 ,  H01L21/28

    CPC classification number: H01L21/823437 ,  H01L29/66181 ,  H01L29/94

    Abstract: An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a gate structure disposed over a substrate; a source region and a drain region disposed in the substrate, wherein the gate structure interposes the source region and the drain region; and at least one post feature embedded in the gate structure.

    Abstract translation: 公开了一种集成电路器件及其制造方法。 在一个示例中，集成电路器件包括设置在衬底上的栅极结构; 设置在所述基板中的源极区域和漏极区域，其中所述栅极结构插入所述源极区域和所述漏极区域; 以及嵌入在门结构中的至少一个后置特征。

    BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH
    105.
    发明申请
    BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH 有权
    包含有效装置的BEOL结构和机械强度

    公开(公告)号：US20120306018A1

    公开(公告)日：2012-12-06

    申请号：US13149797

    申请日：2011-05-31

    Applicant: Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    Inventor： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    IPC: H01L29/772 ,  H01L29/92 ,  H01L21/20 ,  H01L29/02

    CPC classification number: H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

    Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

    Abstract translation: 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

    STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET
    106.
    发明申请
    STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET 审中-公开
    用于制造PIN异构TFET的结构

    公开(公告)号：US20120298963A1

    公开(公告)日：2012-11-29

    申请号：US13571392

    申请日：2012-08-10

    Applicant: Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

    Inventor： Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L29/772

    CPC classification number: H01L29/7391 ,  H01L21/2007 ,  H01L21/76254 ,  H01L29/66227

    Abstract: A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.

    Abstract translation: 用于制造PiN异质结隧道场效应晶体管（TFET）的结构包括：硅晶片，其包括对准沟槽，p型硅锗（SiGe）区域和p型SiGe区域下方的氢注入区域，以及 所述对准沟槽将所述硅晶片分成上硅区域和下硅区域，其中所述上硅区域包括所述对准沟槽和所述p型SiGe区域; 以及位于对准沟槽和p型SiGe区域上方的第一氧化物层，其填充对准沟槽并且结合到位于处理晶片上的第二氧化物层; 其中所述对准沟槽被配置为将包括所述PiN异质结TFET的器件的布线电平对准到所述p型SiGe区域。

    PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE
    108.
    发明申请
    PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE 有权
    制造具有这种应力结构的应力分布结构和半导体器件的工艺

    公开(公告)号：US20120292638A1

    公开(公告)日：2012-11-22

    申请号：US13110294

    申请日：2011-05-18

    Applicant: Chin-I LIAO ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

    Inventor： Chin-I LIAO ,  Ching-Hong Jiang ,  Ching-I Li ,  Shu-Yen Chan ,  Chin-Cheng Chien

    IPC: H01L29/772 ,  H01L21/336

    CPC classification number: H01L29/7842 ,  H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.

    Abstract translation: 制造应力提供结构的方法被应用于半导体器件的制造。 首先，提供具有沟道结构的衬底。 通过化学气相沉积在含卤素的环境中在衬底上形成氮化硅层。 执行蚀刻处理以部分地去除氮化硅层以暴露基板的表面的一部分在通道结构旁边。 蚀刻衬底的暴露表面以在衬底中形成凹陷。 然后，将衬底在750℃和820℃之间的温度下进行热处理。在对衬底进行热处理之后，在凹部中填充应力提供材料，以在凹部内形成应力提供结构。 半导体器件包括衬底，凹部和应力提供结构。 凹槽具有圆形的内表面。 应力提供结构具有圆形外表面。

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