公开(公告)号：US08709910B2

公开(公告)日：2014-04-29

申请号：US13459262

申请日：2012-04-30

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

IPC分类号： H01L21/76

CPC分类号： H01L21/0237 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/66795

摘要： A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.

摘要翻译： 半导体工艺包括以下步骤。 提供半导体衬底。 半导体衬底具有图案化隔离层，并且图案化隔离层具有暴露半导体衬底的硅区域的开口。 在开口的侧壁上形成富硅层。 执行外延工艺以在开口中的硅区域上形成外延结构。

公开(公告)号：US08664069B2

公开(公告)日：2014-03-04

申请号：US13440978

申请日：2012-04-05

申请人： Chin-I Liao ,  Chin-Cheng Chien

发明人： Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

摘要翻译： 半导体结构包括栅极结构，外延层和含碳硅锗覆盖层。 栅极结构位于衬底上。 外延层位于栅极结构旁边的衬底中。 含碳硅锗覆盖层位于外延层上。 否则，还提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US20130341638A1

公开(公告)日：2013-12-26

申请号：US13530127

申请日：2012-06-22

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC分类号： H01L29/772 ,  H01L21/20 ,  H01L29/161

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20130092954A1

公开(公告)日：2013-04-18

申请号：US13274357

申请日：2011-10-17

申请人： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

发明人： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/04

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

摘要： A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

摘要翻译： 一种制造应变通道半导体结构的方法包括提供衬底，在所述衬底上形成至少一个栅极结构，执行蚀刻工艺以在所述衬底的所述栅极结构的相对侧形成两个凹槽，所述凹槽的侧壁为凹面 在所述栅极结构的方向上并相对于水平面形成夹角，并且执行预烘烤处理以改变凹部，使得所述凹部的侧壁和水平面之间的所述夹角增加。

公开(公告)号：US20130052778A1

公开(公告)日：2013-02-28

申请号：US13216259

申请日：2011-08-24

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/66628

摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

摘要翻译： 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

公开(公告)号：US20130026538A1

公开(公告)日：2013-01-31

申请号：US13189570

申请日：2011-07-25

申请人： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

发明人： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC分类号： H01L29/165 ,  H01L29/78

CPC分类号： H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

摘要翻译： 具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。 外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。 未掺杂的帽层还包括第一半导体材料和第二半导体材料。 外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

公开(公告)号：US07858529B2

公开(公告)日：2010-12-28

申请号：US11611891

申请日：2006-12-18

申请人： Chin-I Liao ,  Chin-Cheng Chien

发明人： Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02057 ,  H01L21/3065 ,  H01L29/0688 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7836 ,  H01L29/7848

摘要： The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.

摘要翻译： 本发明的方法包括提供具有凹部的半导体衬底; 在所述半导体衬底上执行预清洁步骤; 以及在半导体衬底上执行第一还原步骤，横向蚀刻步骤和第二还原步骤。 MOS结构包括半导体衬底，半导体衬底上的栅极结构，具有延伸到栅极结构下方和下方的尖端部分的一对凹部以及填充凹部的应变材料。 通过包括横向蚀刻步骤的方法处理的半导体衬底内的凹部形成喙部。

公开(公告)号：US08710632B2

公开(公告)日：2014-04-29

申请号：US13606007

申请日：2012-09-07

申请人： Tien-Wei Yu ,  Chin-Cheng Chien ,  I-Ming Lai ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Fong-Lung Chuang ,  Chin-I Liao ,  Kuan-Yu Lin

发明人： Tien-Wei Yu ,  Chin-Cheng Chien ,  I-Ming Lai ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Fong-Lung Chuang ,  Chin-I Liao ,  Kuan-Yu Lin

IPC分类号： H01L21/02

CPC分类号： H01L21/02639 ,  C30B25/165 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.

摘要翻译： 一种制备化合物半导体外延结构的方法包括以下步骤。 首先，在基板上形成第一复合外延层。 然后，进行连续的外延沉积工艺以在第一复合外延层上形成第二化合物外延层，使得第二化合物外延层具有线性降低的金属浓度梯度。 之后，在第二复合外延层上形成半导体材料层。

公开(公告)号：US20130330898A1

公开(公告)日：2013-12-12

申请号：US13494016

申请日：2012-06-12

申请人： Chin-I Liao ,  Chin-Cheng Chien

发明人： Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/4966 ,  H01L29/66636 ,  H01L29/7848

摘要： A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.

摘要翻译： MOS晶体管工艺包括以下步骤。 在基板上形成栅极结构。 在栅极结构旁边的衬底中形成源极/漏极。 在形成源极/漏极之后，（1）在栅极结构旁边的基板中形成至少一个凹部。 在凹部中形成外延结构。 （2）可以进行清洁处理以清洁栅极结构旁边的基板的表面。 在栅极结构旁边的衬底中形成外延结构。

公开(公告)号：US20130264613A1

公开(公告)日：2013-10-10

申请号：US13440978

申请日：2012-04-05

申请人： Chin-I Liao ,  Chin-Cheng Chien

发明人： Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

摘要翻译： 半导体结构包括玛瑙结构，外延层和含碳硅锗覆盖层。 栅极结构位于衬底上。 外延层位于栅极结构旁边的衬底中。 含碳硅锗覆盖层位于外延层上。 否则，还提供了用于形成所述半导体结构的半导体工艺。