公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

Applicant: Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

Inventor： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC: H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US09070784B2

公开(公告)日：2015-06-30

申请号：US13189232

申请日：2011-07-22

Applicant: Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

Inventor： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/3212 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0642

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括衬底，N金属栅电极和P金属栅电极。 衬底包括围绕P活性区域和N-活性区域的隔离区域。 所述N-金属栅电极包括在所述N-活性区上的第一金属组合物。 P型金属栅电极包括位于P有源区上的本体部分和在隔离区上方的端盖部分。 端盖部分包括第一金属组合物，并且本体部分包含不同于第一金属组合物的第二金属组合物。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

Applicant: Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

Inventor： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

Abstract translation: 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08697517B2

公开(公告)日：2014-04-15

申请号：US12724904

申请日：2010-03-16

Applicant: Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

Inventor： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC: H01L21/8242

CPC classification number: H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

Abstract translation: 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光致抗蚀剂（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

Applicant: Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

Inventor： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC: H01L21/76

CPC classification number: H01L21/3081 ,  H01L21/76232

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract translation: 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US08525270B2

公开(公告)日：2013-09-03

申请号：US12713395

申请日：2010-02-26

Applicant: Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

Inventor： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC: H01L21/70

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

Abstract: The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

Abstract translation: 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US20120319180A1

公开(公告)日：2012-12-20

申请号：US13162453

申请日：2011-06-16

Applicant: Harry-Hak-Lay Chuang ,  Ming Zhu

Inventor： Harry-Hak-Lay Chuang ,  Ming Zhu

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/823437 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a gate structure disposed over a substrate; a source region and a drain region disposed in the substrate, wherein the gate structure interposes the source region and the drain region; and at least one post feature embedded in the gate structure.

Abstract translation: 公开了一种集成电路器件及其制造方法。 在一个示例中，集成电路器件包括设置在衬底上的栅极结构; 设置在所述基板中的源极区域和漏极区域，其中所述栅极结构插入所述源极区域和所述漏极区域; 以及嵌入在门结构中的至少一个后置特征。

公开(公告)号：US08304840B2

公开(公告)日：2012-11-06

申请号：US12846261

申请日：2010-07-29

Applicant: Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

Inventor： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC: H01L21/02 ,  H01L21/70 ,  H01L27/088

CPC classification number: H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

Abstract translation: 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

公开(公告)号：US08183644B1

公开(公告)日：2012-05-22

申请号：US13025956

申请日：2011-02-11

Applicant: Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

Inventor： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

IPC: H01L21/027

CPC classification number: H01L21/823842 ,  H01L21/823871

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，其包括P活性区域，N活性区域和插入在P-活性区域和N - 活性区域之间的隔离区域; 在P-活性区域上的P金属栅极电极，其在隔离区域上延伸; 以及在所述N-有源区上具有第一宽度的N-金属栅电极，其在所述隔离区上延伸，并且在所述隔离区中具有与所述P金属栅电极电接触的接触部，其中所述接触部具有第二宽度 大于第一宽度。

公开(公告)号：US20120001259A1

公开(公告)日：2012-01-05

申请号：US12830107

申请日：2010-07-02

Applicant: Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

Inventor： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

Abstract translation: 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。