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    Semiconductor device and method of manufacturing semiconductor device
    103.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US09087898B2

    公开(公告)日：2015-07-21

    申请号：US13627183

    申请日：2012-09-26

    申请人： FUJITSU SEMICONDUCTOR LIMITED

    发明人： Eiji Yoshida

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/74 ,  H01L21/308 ,  H01L29/66

    CPC分类号： H01L29/7833 ,  H01L21/3081 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0638 ,  H01L29/665

    摘要： A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

    摘要翻译： 半导体器件包括限定第一区域的第一器件隔离绝缘膜，形成在第一区域中的第一导电类型的第一导电层，形成在半导体衬底上方的半导体层，并且包括第一导电类型的第二导电层， 连接到第一导电层和连接到第一导电层的第一导电类型的第三导电层，形成在半导体层中并将第二导电层和第三导电层彼此隔离的第二器件隔离绝缘膜，栅极 形成在第二导电层上方的绝缘膜，以及形成在栅极绝缘膜之上并通过第三导电层电连接到第一导电层的栅电极。

    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING
    104.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING 有权
    半导体器件结构及其形成方法

    公开(公告)号：US20150200134A1

    公开(公告)日：2015-07-16

    申请号：US14153848

    申请日：2014-01-13

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Zhuo-Cang YANG ,  Chih-Kuan CHEN

    IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L21/02 ,  H01L27/06

    CPC分类号： H01L21/76877 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/8605 ,  H01L29/8611

    摘要： Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer.

    摘要翻译： 提供半导体器件结构的实施例和形成半导体器件结构的方法。 半导体器件结构包括具有顶表面，底表面和侧表面的绝缘层。 半导体器件结构还包括形成在第一绝缘层的底表面上的第一半导体衬底。 半导体器件结构还包括仅在第一半导体衬底上与绝缘层的侧表面相邻形成的导电特征。 此外，半导体器件结构包括形成在绝缘层的顶表面上的第二半导体衬底。 第二半导体衬底包括直接在绝缘层上方形成的器件形成区域，使得器件形成区域的突出区域位于绝缘层的内部。

    ISOLATION TRENCH FILL USING OXIDE LINER AND NITRIDE ETCH BACK TECHNIQUE WITH DUAL TRENCH DEPTH CAPABILITY
    105.
    发明申请
    ISOLATION TRENCH FILL USING OXIDE LINER AND NITRIDE ETCH BACK TECHNIQUE WITH DUAL TRENCH DEPTH CAPABILITY 有权
    使用氧化锌衬垫和氮化钛回填技术的隔离透气膜，具有双重深度深度能力

    公开(公告)号：US20150194336A1

    公开(公告)日：2015-07-09

    申请号：US14589432

    申请日：2015-01-05

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Xianfeng Zhou

    IPC分类号： H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/06

    CPC分类号： H01L29/0653 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/11548 ,  H01L29/0649

    摘要： An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

    摘要翻译： 在具有较小隔离沟槽和大隔离沟槽的衬底上形成氧化物层。 在氧化物层上形成氮化物层，使得其完全填充较小的隔离沟槽并对较大的隔离沟槽进行排列。 蚀刻氮化物层以在更小的隔离沟槽中的氮化物层中形成凹陷，同时完全去除衬在较大隔离沟槽的氮化物层的至少一部分。 在衬底上沉积一层HDP氧化物，完全填充越来越小的隔离沟槽。 HDP氧化物层平坦化到衬底的上表面。 在沉积HDP氧化物之前，可以通过在氮化物层被回蚀后进行蚀刻步骤来形成更深的较大的隔离沟槽。

    Scaling of bipolar transistors
    107.
    发明授权
    Scaling of bipolar transistors 有权
    双极晶体管的缩放

    公开(公告)号：US09076810B2

    公开(公告)日：2015-07-07

    申请号：US14508011

    申请日：2014-10-07

    申请人： International Business Machines Corporation

    发明人： Alvin J. Joseph ,  Ramana M. Malladi ,  James A. Slinkman

    IPC分类号： H01L21/331 ,  H01L29/66 ,  G06F17/50 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L27/02

    CPC分类号： H01L29/66272 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8249 ,  H01L27/0207 ,  H01L29/7322 ,  Y02P90/265

    摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.

    摘要翻译： 双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。 设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计 双极晶体管。

    ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
    108.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    电子设备及其制造方法

    公开(公告)号：US20150179259A1

    公开(公告)日：2015-06-25

    申请号：US14538715

    申请日：2014-11-11

    申请人： SK hynix Inc.

    发明人： Jung-Nam Kim ,  Jong-Han Shin ,  Sung-Jun Kim ,  Sang-Soo Kim

    IPC分类号： G11C14/00 ,  G06F12/08 ,  G11C7/10 ,  H01L27/105

    CPC分类号： G11C7/1003 ,  H01L21/76229 ,  H01L27/1052

    摘要： An electronic device including a semiconductor memory is provided, wherein the semiconductor memory comprises: a substrate in which first to third regions are provided; first to third trenches formed in the first to third regions, respectively, and having a different line width from each other; and first to third device isolation layers formed in the first to third trenches, respectively, wherein the first device isolation layer includes a stack structure of a first insulation layer and a second insulation layer, the second device isolation layer includes the first insulation layer formed over a part of a bottom and one sidewall of the second trench, the second insulation layer having a stepped type and a third insulation layer which is formed over the second insulation layer, and the third device isolation layer includes a stack structure of the first to third insulation layers.

    摘要翻译： 提供一种包括半导体存储器的电子设备，其中半导体存储器包括：提供第一至第三区域的基板; 第一至第三沟槽分别形成在第一至第三区域中，并且具有彼此不同的线宽度; 以及分别形成在第一至第三沟槽中的第一至第三器件隔离层，其中第一器件隔离层包括第一绝缘层和第二绝缘层的堆叠结构，第二器件隔离层包括形成在第一至第三沟槽上的第一绝缘层 所述第二沟槽的底部和一个侧壁的一部分，所述第二绝缘层具有阶梯型和形成在所述第二绝缘层上的第三绝缘层，所述第三器件隔离层包括第一至第三绝缘层的堆叠结构 绝缘层。

    Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof
    110.
    发明申请
    Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof 审中-公开
    制造半导体器件及其结构的隔离区域的方法

    公开(公告)号：US20150137309A1

    公开(公告)日：2015-05-21

    申请号：US14559801

    申请日：2014-12-03

    申请人： Infineon Technologies AG

    发明人： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

    IPC分类号： H01L29/06 ,  H01L21/02

    CPC分类号： H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

    摘要翻译： 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。