公开(公告)号：US10332830B2

公开(公告)日：2019-06-25

申请号：US15592488

申请日：2017-05-11

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Wei-Che Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure. the third semiconductor package is coupled to the second RDL structure by second vias passing through a second molding compound between the third semiconductor package and the second RDL structure.

公开(公告)号：US10109608B2

公开(公告)日：2018-10-23

申请号：US15189369

申请日：2016-06-22

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Tai-Yu Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

公开(公告)号：US10090375B2

公开(公告)日：2018-10-02

申请号：US15450411

申请日：2017-03-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Cheng-Chou Hung

IPC: H01L27/01 ,  H01L49/02 ,  H01L23/00 ,  H01L23/66

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

公开(公告)号：US10032756B2

公开(公告)日：2018-07-24

申请号：US15071573

申请日：2016-03-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng

IPC: H01L25/16 ,  H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

公开(公告)号：US20170243814A1

公开(公告)日：2017-08-24

申请号：US15590021

申请日：2017-05-09

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Tzu-Hung Lin

IPC: H01L23/498 ,  H01L23/482

CPC classification number: H01L23/49811 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/09 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579

Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.

公开(公告)号：US09704836B2

公开(公告)日：2017-07-11

申请号：US15014636

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

IPC: H01L23/485 ,  H01L25/10 ,  H01L21/02 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

公开(公告)号：US09679842B2

公开(公告)日：2017-06-13

申请号：US14741820

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Wei-Che Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.

公开(公告)号：US09679830B2

公开(公告)日：2017-06-13

申请号：US14830727

申请日：2015-08-19

Applicant: MEDIATEK INC.

Inventor： Jia-Wei Fang ,  Tzu-Hung Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/09 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579

Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.

公开(公告)号：US09659893B2

公开(公告)日：2017-05-23

申请号：US14826471

申请日：2015-08-14

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/50

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/183 ,  H01L2924/35 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.

公开(公告)号：US09553040B2

公开(公告)日：2017-01-24

申请号：US13835701

申请日：2013-03-15

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tzu-Hung Lin ,  Ta-Jen Yu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括半导体封装，其包括具有管芯附接表面的衬底。 模具通过导电柱凸块安装在基板的芯片附着表面上。 芯片包括电耦合到导电柱凸起的金属焊盘，其中金属焊盘具有基本上垂直于第一边缘的第一边缘和第二边缘，其中第一边缘的长度与第二边缘的长度不同于 平面图。