公开(公告)号：US20240282569A1

公开(公告)日：2024-08-22

申请号：US18171508

申请日：2023-02-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chen Lo ,  Ding-Kang Shih ,  Tsungyu Hung ,  Chia-Ling Pai ,  Pang-Yen Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/02068 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L23/5226

摘要： In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

公开(公告)号：US20240282171A1

公开(公告)日：2024-08-22

申请号：US18588209

申请日：2024-02-27

申请人： Everi Payments Inc.

发明人： Adam Fong ,  Michael Elston

IPC分类号： G07F17/32 ,  A01D41/127 ,  A01D41/14 ,  A63F13/71 ,  G06Q50/02 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC分类号： G07F17/3244 ,  A01D41/1274 ,  A01D41/141 ,  A01D41/145 ,  A63F13/71 ,  G06Q50/02 ,  G07F17/3218 ,  G07F17/3225 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/312 ,  H10B12/50

摘要： Relative to a gaming system, a jackpot or game win processing device and server are configured to receive acknowledgement from a player regarding a gaming win award, such as input to the game win processing device of a signature by the player to gaming win forms. In response, the server is configured to generate at least one gaming win reporting form, such as a W2G, to store that form and provide access to the form, such as by emailing the form to the player or allowing the player to access the form via a portal.

公开(公告)号：US12068378B2

公开(公告)日：2024-08-20

申请号：US18360085

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yu Huang ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L29/4175 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775

摘要： A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

公开(公告)号：US20240274532A1

公开(公告)日：2024-08-15

申请号：US18326218

申请日：2023-05-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Ching Huang ,  Yu-Sheng Chen ,  Yi Ching Ong

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30

摘要： Various embodiments of the present disclosure are directed towards an integrated chip comprising a ferroelectric structure disposed between a first conductive interconnect structure and a second conductive interconnect structure. The first conductive interconnect structure overlies a substrate. The second conductive interconnect structure overlies the first conductive interconnect structure. The second conductive interconnect structure comprises a conductive wire segment directly overlying a conductive via segment. The ferroelectric structure continuously extends along opposing sidewalls and a bottom surface of the conductive wire segment and along opposing sidewalls and a bottom surface of the conductive via segment

公开(公告)号：US20240274191A1

公开(公告)日：2024-08-15

申请号：US18356825

申请日：2023-07-21

申请人： SANDISK TECHNOLOGIES LLC

发明人： Koichi MATSUNO ,  Johann ALSMEIER

IPC分类号： G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： A memory device includes a first-tier alternating stack of first insulating layers and electrically conductive layers located over a substrate, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, a memory stack structure vertically extending through the first-tier alternating stack and the second-tier alternating stack, and a first support and contact assembly vertically extending through the first-tier alternating stack and the second-tier alternating stack. The first support and contact assembly includes a first contact via structure contacting an annular top surface of an electrically conductive layer, a first dielectric pillar structure underlying the reference-level electrically conductive layer, and a first-tier dielectric spacer that laterally surrounds the first contact via structure.

公开(公告)号：US12063773B2

公开(公告)日：2024-08-13

申请号：US17589580

申请日：2022-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC分类号： G11C17/00 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/528 ,  H10B20/20

CPC分类号： H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/528

摘要： A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

公开(公告)号：US12062617B2

公开(公告)日：2024-08-13

申请号：US17562127

申请日：2021-12-27

申请人： Samsung Electronics Co., Ltd.

发明人： Joonsung Kim

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/522

CPC分类号： H01L23/5383 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5386 ,  H01L24/08 ,  H01L23/3171 ,  H01L2224/08235

摘要： A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

公开(公告)号：US12062607B2

公开(公告)日：2024-08-13

申请号：US17958986

申请日：2022-10-03

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Chan H. Yoo

IPC分类号： H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01M50/414 ,  H05K9/00

CPC分类号： H01L23/5226 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/528 ,  H01L25/0657 ,  H01M50/414 ,  H05K9/0083 ,  H01H2227/014 ,  H01L2224/80855

摘要： Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

公开(公告)号：US12062606B2

公开(公告)日：2024-08-13

申请号：US17337212

申请日：2021-06-02

申请人： Samsung Electronics Co., Ltd.

发明人： Sujeong Kim ,  Inmo Kim

IPC分类号： H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC分类号： H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

摘要： A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

公开(公告)号：US12062578B2

公开(公告)日：2024-08-13

申请号：US17838645

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC分类号： H01L27/01 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

摘要： A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.