公开(公告)号：US20150044866A1

公开(公告)日：2015-02-12

申请号：US14454023

申请日：2014-08-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Christophe BOUVIER ,  Gabriel PARES

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.

Abstract translation: 一种用于制造由一组支撑件（W）形成的微电子器件的方法，每个支撑件设置有一个或多个电子部件（C），并且包括由第一盲导电通孔（171b，472）形成的导电结构（170,470）和 具有较大高度的第二盲导电通孔（171a，473），第一通孔和第二通孔连接在一起。

公开(公告)号：US08928128B2

公开(公告)日：2015-01-06

申请号：US13405721

申请日：2012-02-27

Applicant: Sampath K. V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sampath K. V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/3025

Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Abstract translation: 这里公开了位于顶部有源管芯和底部有源管芯之间的屏蔽插入器的各种实现方式，用于屏蔽活动管芯免受电磁噪声。 一种实现方式包括内插器电介质层，内插电介质层内的穿硅通孔（TSV）和电磁屏蔽。 TSV将电磁屏蔽连接到第一固定电位。 电磁屏蔽可以包括横跨屏蔽插入件横向延伸的导电层格。 屏蔽插入器还可以包括连接到另一个固定电位的另一个电磁屏蔽。

公开(公告)号：US20150001689A1

公开(公告)日：2015-01-01

申请号：US13931902

申请日：2013-06-29

Applicant: Edmund Goetz ,  Bernd Memmler ,  Jan-Erik Mueller ,  Peter Baumgartner

Inventor： Edmund Goetz ,  Bernd Memmler ,  Jan-Erik Mueller ,  Peter Baumgartner

IPC: H01L23/552 ,  H01L25/00

CPC classification number: H04B1/40 ,  H01L21/6835 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6644 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.

Abstract translation: 描述半导体封装内的射频屏蔽。 在一个示例中，多芯片封装在数字芯片和射频芯片之间具有数字芯片，射频芯片和隔离层。 盖子包围数字芯片和射频芯片。

公开(公告)号：US08912581B2

公开(公告)日：2014-12-16

申请号：US13415906

申请日：2012-03-09

Applicant: Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Feng Wei Kuo ,  Ho-Hsiang Chen ,  Chin-Wei Kuo

Inventor： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Feng Wei Kuo ,  Ho-Hsiang Chen ,  Chin-Wei Kuo

IPC: H01L29/80 ,  H01L39/00 ,  H01L29/40 ,  H01L23/60

CPC classification number: H01L23/60 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L25/0657 ,  H01L2223/6627 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.

Abstract translation: 用于半导体RF和无线电路的传输线结构及其形成方法。 传输线结构包括具有包括第一衬底，第一绝缘层和接地平面的第一裸片的实施例，以及包括第二衬底，第二绝缘层和信号传输线的第二裸片。 第二管芯可以位于第一管芯的上方并与之隔开。 在第一管芯的接地面和第二管芯的信号传输线之间设置底部填充物。 总的来说，第一和第二模具和底部填充物的接地平面和传输线形成紧凑的传输线结构。 在一些实施例中，传输线结构可用于微波应用。

公开(公告)号：US20140291821A1

公开(公告)日：2014-10-02

申请号：US14304016

申请日：2014-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-sang SONG

IPC: H01L23/58 ,  H01L23/552

CPC classification number: H01L23/585 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24227 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/078 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package and method of manufacture are provided. The semiconductor package may include a package substrate, a semiconductor chip, a molding member and a grounding member. The package substrate may include a ground pad and a signal pad. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the signal pad of the package substrate. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The grounding member may be arranged on a surface of the molding member. The grounding member may be electrically connected with the ground pad.

Abstract translation: 提供半导体封装和制造方法。 半导体封装可以包括封装衬底，半导体芯片，模制构件和接地构件。 封装衬底可以包括接地焊盘和信号焊盘。 半导体芯片可以布置在封装衬底的上表面上。 半导体芯片可以与封装衬底的信号焊盘电连接。 模制构件可以形成在封装衬底的上表面上以覆盖半导体芯片。 接地构件可以布置在模制构件的表面上。 接地构件可以与接地垫电连接。

公开(公告)号：US20140284763A1

公开(公告)日：2014-09-25

申请号：US14203506

申请日：2014-03-10

Applicant: Realtek Semiconductor Corp.

Inventor： Ta-Hsun Yeh

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/645 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).

Abstract translation: 本发明提供集成电感器和集成电感器制造方法。 集成电感器包括：半导体衬底，电感器和再分配层（RDL）。 电感器形成在半导体衬底之上。 RDL形成在电感器上方，并具有特定的图案以形成图案化的接地屏蔽（PGS）。 集成电感器制造方法包括：形成半导体衬底; 在半导体衬底上形成电感器; 以及在电感器上形成具有特定图案的再分布层（RDL）以形成图案化接地屏蔽（PGS）。

公开(公告)号：US20140252568A1

公开(公告)日：2014-09-11

申请号：US13794487

申请日：2013-03-11

Applicant: QUALLCOMM INCORPORATED

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim ,  Changhan Yun

IPC: H01L23/552 ,  H01L21/82

CPC classification number: H01L23/552 ,  H01L21/82 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K9/0007 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Abstract translation: 一个特征涉及包括衬底和耦合到衬底的电磁干扰（EMI）屏蔽）的多芯片封装。 至少一个集成电路耦合到衬底的第一表面。 EMI屏蔽包括被配置为将封装与射频辐射屏蔽的金属外壳，耦合到金属外壳的内表面的至少一部分的电介质层和多个信号线。 信号线耦合到电介质层，并通过电介质层与金属外壳电隔离。 至少一个其它集成电路耦合到EMI屏蔽的内表面，并且EMI屏蔽的内表面的至少一部分面向基板的第一表面。 信号线被配置为向第二电路部件提供电信号。

公开(公告)号：US08791550B1

公开(公告)日：2014-07-29

申请号：US13741947

申请日：2013-01-15

Applicant: International Business Machines Corporation

Inventor： Xiaoxiong Gu ,  Michael Mcallister

IPC: H01L21/40 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate.

公开(公告)号：US20140197522A1

公开(公告)日：2014-07-17

申请号：US13741947

申请日：2013-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xiaoxiong Gu ,  Michael Mcallister

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate.

公开(公告)号：US20140021591A1

公开(公告)日：2014-01-23

申请号：US13728112

申请日：2012-12-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Shih Sung ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Abstract translation: 提供一种半导体元件，包括：具有形成在其中的多个第一导电通孔和第二导电通孔的基板; 形成在所述基板上并具有电连接到所述第一导电通孔的多个导电焊盘的再分布层; 以及形成在再分布层上并电连接到第二导电通孔的金属层。 金属层还具有多个开口，用于再分配层的导电焊盘从开口暴露而不电连接第一金属层。 因此，金属层和第二导电贯通孔形成能够防止电磁波进入或离开半导体元件的再分布层或侧面的屏蔽结构，从而有效地屏蔽电磁干扰。