公开(公告)号：US20180156866A1

公开(公告)日：2018-06-07

申请号：US15368480

申请日：2016-12-02

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Teresa Louise Mclaurin ,  Richard Slobodnik ,  Frank David Frederick ,  Kartikey Jani

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318583 ,  G11C2029/3202

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

公开(公告)号：US20180080973A1

公开(公告)日：2018-03-22

申请号：US15529559

申请日：2016-07-01

Applicant: BOE Technology Group Co., Ltd. ,  Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Inventor： Miao Zhang ,  Jinliang Liu ,  Mo Chen ,  Jing Sun ,  Songmei Sun

IPC: G01R31/26 ,  G09G3/36 ,  G11C19/28

CPC classification number: G01R31/2601 ,  G01R31/00 ,  G09G3/006 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28 ,  G11C19/287 ,  G11C29/00 ,  G11C29/021 ,  G11C29/22 ,  G11C29/32 ,  G11C29/50012 ,  G11C29/56012 ,  G11C2029/3202 ,  G11C2029/5602

Abstract: The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

公开(公告)号：US20170316834A1

公开(公告)日：2017-11-02

申请号：US15220110

申请日：2016-07-26

Applicant: SanDisk Technologies LLC

Inventor： Jonathan Huynh ,  Jongmin Park

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/3422 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/1202 ,  G11C2029/3202 ,  G11C2029/5006

Abstract: Techniques are presented for determining current leakage from a memory array or other circuit based on a low voltage path. For example, the technique can be applied to determine word line to word line leakage. By looking at a count for the clock used in regulating the low voltage output node, the amount of leakage can be determined. The leakage determination can be performed as part of test process or during normal memory operations.

公开(公告)号：US20170140838A1

公开(公告)日：2017-05-18

申请号：US15420720

申请日：2017-01-31

Applicant: STMicroelectronics International N.V

Inventor： Swapnil Bahl ,  Shray Khullar

IPC: G11C29/32 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/34 ,  G06F11/25

CPC classification number: G11C29/32 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G06F11/25 ,  G11C29/34 ,  G11C2029/3202

Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

公开(公告)号：US20170025187A1

公开(公告)日：2017-01-26

申请号：US15282932

申请日：2016-09-30

Applicant: Cryptography Research, Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

Abstract translation: 易失性存储器件可以在通过第一信号路径耦合到存储器控制器的第一存储器模块上。 非易失性存储器件可以位于通过第二信号路径耦合到第一存储器模块的第二存储器模块上。 用于非易失性存储器件的存储事务可以使用第一信号路径从存储器控制器传送到易失性存储器件中的至少一个，并且与存储器事务相关联的数据将从至少一个易失性存储器件写入到 使用第二信号路径的非易失性存储装置和控制信号。 基于从存储位置读取的测试值与存储值的比较，鉴于非易失性存储器件中的缺陷的检测，缺陷电路可以产生控制信号。

公开(公告)号：US09460021B2

公开(公告)日：2016-10-04

申请号：US14883916

申请日：2015-10-15

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/12 ,  G11C29/00 ,  G06F3/06

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.

Abstract translation: 对应于第一存储器层级的易失性存储器件可以在通过第一信号路径耦合到存储器控制器的第一存储器模块上。 对应于第二存储器层级的非易失性存储器件可以在通过第二信号路径耦合到第一存储器模块的第二存储器模块上。 非易失性存储器件的存储器事务可以使用第一信号路径从存储器控制器传送到第一存储器层级，并且与存储器事务的累积有关的数据可以从第一存储器层次写入第二存储器层次， 第二信号路径和第一和第二控制信号。 考虑到磨损的检测可以产生第一控制信号，并且可以考虑到缺陷的检测而产生第二控制信号。

公开(公告)号：US09214449B2

公开(公告)日：2015-12-15

申请号：US13367026

申请日：2012-02-06

Applicant: Brent Keeth

Inventor： Brent Keeth

IPC: G01R31/26 ,  H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  G11C29/02 ,  G11C29/00 ,  G11C5/04 ,  G11C29/32

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C29/02 ,  G11C29/022 ,  G11C29/70 ,  G11C2029/3202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1531 ,  H01L2924/00

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract translation: 一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为 检查连接中的缺陷并修复连接的缺陷。

公开(公告)号：US09195602B2

公开(公告)日：2015-11-24

申请号：US12529323

申请日：2008-03-19

Applicant: Craig Hampel ,  Mark Horowitz

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/12 ,  G11C29/00

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

Abstract translation: 公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。 第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。 模块中包含第一个集成电路缓冲器。 该系统具有定义第二存储器层级的第二组非易失性存储器件。 第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。 第二模块包括第二集成电路缓冲装置。 该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

公开(公告)号：US09188642B2

公开(公告)日：2015-11-17

申请号：US13975277

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ritu Chaba ,  Lakshmikantha Holla Vakwadi

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/36

CPC classification number: G01R31/318541 ,  G01R31/318597 ,  G11C29/32 ,  G11C29/36 ,  G11C2029/3202 ,  G11C2029/3602

Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

Abstract translation: 提供了在功能模式和ATPG扫描模式下操作装置的方法以及用于功能模式和ATPG扫描模式的装置。 该装置包括一组锁存器，其包括第一锁存器和第二锁存器。 第一个锁存器作为主锁存器操作，第二个锁存器在功能模式下作为主锁存器运行。 第一个锁存器作为触发器的主锁存器操作，第二个锁存器在ATPG扫描模式下作为触发器的从锁存器操作。 在一种配置中，该装置包括至少包括第一和第二锁存器的多个锁存器，每个锁存器的输出耦合到数字电路，该装置包括多个功能输入，并且每个功能输入是 输入到数字电路。

公开(公告)号：US20150162097A1

公开(公告)日：2015-06-11

申请号：US14527352

申请日：2014-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin Eckert ,  Otto Torreiter ,  Christian Zoelin

IPC: G11C29/12

CPC classification number: G11C29/12015 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/31701 ,  G01R31/31721 ,  G01R31/3187 ,  G06F1/3275 ,  G06F1/3287 ,  G06F11/1068 ,  G06F11/2236 ,  G06F11/27 ,  G11C29/26 ,  G11C29/50 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/3202 ,  G11C2029/3602

Abstract: The invention relates to a method for performing an array built-in self-test (ABIST) on an electronic circuit (100), the electronic circuit (100) comprising a memory (110) with at least two memory arrays (111-115) and at least two array built-in self-test engines (116-120), wherein each automatic built-in self-test engine (116-120) is associated with a different memory array (111-115) and wherein each array built-in self-test engine (116-120) is associated with a programmable delay unit (DU1-DU5), the method comprising the following steps:determine at least one delay value (dn), the delay value (dn) corresponding to an array built-in self-test engine (116-120) and the delay value (dn) depending on the execution time (tdn) for testing the memory array (111-115) associated with the array built-in self-test engine (116-120); provide the at least one delay value (dn) to the programmable delay unit (DU1-DU5); and delay the start of the array built-in self-test engine (116-120) depending on the respective delay value (dn).

Abstract translation: 本发明涉及一种用于在电子电路（100）上执行阵列内置自检（ABIST）的方法，所述电子电路（100）包括具有至少两个存储器阵列（111-115）的存储器（110） 和至少两个阵列内置自检引擎（116-120），其中每个自动内置自检引擎（116-120）与不同的存储器阵列（111-115）相关联，并且其中每个阵列被构建 - 自检引擎（116-120）与可编程延迟单元（DU1-DU5）相关联，所述方法包括以下步骤：确定至少一个延迟值（dn），对应于 阵列内置自检引擎（116-120）和延迟值（dn），这取决于用于测试与阵列内置自检引擎相关联的存储器阵列（111-115）的执行时间（tdn） 116-120）; 向所述可编程延迟单元（DU1-DU5）提供所述至少一个延迟值（dn）; 并根据相应的延迟值（dn）延迟阵列内置自检引擎（116-120）的启动。