公开(公告)号：US5600607A

公开(公告)日：1997-02-04

申请号：US435691

申请日：1995-05-05

Applicant: Kiyohiro Furutani ,  Hiroshi Miyamoto

Inventor： Kiyohiro Furutani ,  Hiroshi Miyamoto

IPC: G11C11/401 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C8/00

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/22

Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

Abstract translation: phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。 列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。 差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

公开(公告)号：US5587607A

公开(公告)日：1996-12-24

申请号：US292301

申请日：1994-08-18

Applicant: Kenichi Yasuda ,  Kiyohiro Furutani ,  Hiroshi Miyamoto

Inventor： Kenichi Yasuda ,  Kiyohiro Furutani ,  Hiroshi Miyamoto

IPC: H01L27/04 ,  G11C5/14 ,  G11C7/10 ,  G11C11/401 ,  H01L21/60 ,  H01L21/822 ,  H01L23/495 ,  H01L23/50 ,  H01L27/10 ,  H01L23/48 ,  H01L23/52

CPC classification number: G11C5/14 ,  B82Y10/00 ,  G11C7/1006 ,  G11C7/1045 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  G11C2029/1804 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041

Abstract: A DRAM includes a package, a semiconductor chip housed in the package, and a plurality of leads each disposed from the outside of the package over the periphery of the semiconductor chip. The power supply potential is applied to some of the leads. Corresponding to one power supply lead, one power supply pad and one selection pad are formed. Corresponding to another power supply lead, another power supply pad and another selection pad are formed. Each of these two selection pads is connected or not connected to the corresponding power supply lead by bonding. As a result, one of four word configurations is selected. Since these two selection pads are disposed in the vicinity of the corresponding power supply leads, respectively, the number of times of bonding to one power supply lead is reduced.

Abstract translation: DRAM包括封装，容纳在封装中的半导体芯片，以及从半导体芯片周边的封装外部设置的多个引线。 电源电位适用于某些引线。 对应于一个电源引线，形成一个电源焊盘和一个选择焊盘。 对应于另一个电源引线，形成另一个电源焊盘和另一个选择焊盘。 这两个选择焊盘中的每一个通过结合连接或不连接到相应的电源引线。 结果，选择了四个字配置之一。 由于这两个选择焊盘分别设置在相应的电源引线附近，所以与一个电源引线的接合次数减少。

公开(公告)号：US5586076A

公开(公告)日：1996-12-17

申请号：US304899

申请日：1994-09-13

Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

CPC classification number: G11C11/4096 ,  G11C7/10

Abstract: In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

Abstract translation: 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

公开(公告)号：US5519243A

公开(公告)日：1996-05-21

申请号：US305524

申请日：1994-09-13

Applicant: Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

Inventor： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L29/76 ,  H01L21/265

CPC classification number: H01L27/105 ,  Y10S438/901

Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Abstract translation: 根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。 结果，在半导体衬底中形成电容元件。 可以使半导体器件小型化，并提高元件之间的连接的可靠性。

公开(公告)号：US5375088A

公开(公告)日：1994-12-20

申请号：US149540

申请日：1993-11-09

Applicant: Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

Inventor： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC: G06F11/267 ,  G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/00

CPC classification number: G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G06F11/267

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract translation: 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

公开(公告)号：US5132930A

公开(公告)日：1992-07-21

申请号：US577062

申请日：1990-09-04

Applicant: Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

Inventor： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC: G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/4097 ,  G11C11/4091

Abstract: In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

Abstract translation: 在半导体衬底上形成的金属氧化物半导体（MOS）动态中，第一触发器的数据节点连接到第一对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第二触发器的数据节点连接到第二对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第三触发器的电源节点通过开关连接到第二电源（Vcc）。 第三触发器的数据节点通过第一对传输门耦合到第一对折叠位线，并通过第二对传输门耦合到第二对折叠位线。 耦合第一至第三触发器形成第一读出放大器并且将第二触发器耦合到第三触发器形成第二读出放大器。

公开(公告)号：US5043913A

公开(公告)日：1991-08-27

申请号：US365461

申请日：1989-06-13

Applicant: Kiyohiro Furutani

Inventor： Kiyohiro Furutani

IPC: G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC classification number: G06N3/063

Abstract: Input signals inputted in respective unit circuits forming a synapse array pass through variable connector elements to be integrated into one analog signal, which in turn is converted into a binary associated corresponding signal by an amplifier. Two control signals are produced on the basis of the associated corresponding signal and an educator signal. The two control signals are fed back to the respective unit circuits, to control degrees of electrical coupling of the variable connector elements in the respective unit circuits. Thus, learning of the respective unit circuits is performed.

Abstract translation: 输入到形成突触阵列的各单元电路中的输入信号通过可变连接器元件，以被集成到一个模拟信号中，而该模拟信号又由放大器转换成二进制相关联的对应信号。 基于相应的对应信号和教育者信号产生两个控制信号。 两个控制信号被反馈到相应的单元电路，以控制各个单元电路中的可变连接器元件的电耦合度。 因此，执行各个单元电路的学习。

公开(公告)号：US4788457A

公开(公告)日：1988-11-29

申请号：US94641

申请日：1987-09-09

Applicant: Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

Inventor： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC: G11C11/408 ,  G11C8/10 ,  H03K17/693 ,  H03M7/00 ,  H03K19/096

CPC classification number: H03K17/693 ,  G11C8/10

Abstract: A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.

Abstract translation: 其中用于从存储单元阵列中选择单个字线的行解码器和用于选择单个位线的列解码器的CMOS行解码器电路可以共同地使用内部地址信号传输线。 行解码器电路包括响应于从外部地址信号中选择的地址信号而导通或截止的第一导电类型的一系列MOSFET，提供在电源电位和一系列MOSFET之间的第二导电类型的第二MOSFET 并且具有接收用于提供所述地址信号的解码定时的第一定时信号的栅极，设置在所述一系列MOSFET和所述第二MOSFET之间并具有接收第一操作定时信号的栅极的第一导电类型的第三MOSFET，第四MOSFET 其响应于用于传输第二MOSFET和第三MOSFET的节点的电位的第二操作定时信号而被接通或关断;以及第五MOSFET，其具有接收用于传输字线驱动的第四MOSFET的输出的栅极 信号到相应的字线。

公开(公告)号：US08362827B2

公开(公告)日：2013-01-29

申请号：US12656011

申请日：2010-01-13

Applicant: Kenji Takahashi ,  Kiyohiro Furutani

Inventor： Kenji Takahashi ,  Kiyohiro Furutani

IPC: G05F1/10

CPC classification number: H03K5/133 ,  G06F1/3203 ,  G06F1/3287 ,  H03K19/0013 ,  H03K19/0016 ,  Y02D10/171 ,  Y10T307/696

Abstract: A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.

Abstract translation: 半导体器件包括两个功能电路，PMOS晶体管和NMOS晶体管。 PMOS晶体管控制是否将电源电势输送到功能电路，并且NMOS晶体管控制是否将电源电位GND传送到功能电路。 提供有第三电源电位的外部端子和另一个外部端子被提供有高于第三电源电位的第四电源电位。 电源控制电路将具有第四电源电位作为振幅的控制信号传送到晶体管，以控制晶体管的导电状态或非导通状态。 电源控制电路还将具有作为振幅的第三电源电位的控制信号传送到晶体管以控制NMOS晶体管的导电或非导通状态。

公开(公告)号：US07268612B2

公开(公告)日：2007-09-11

申请号：US11699427

申请日：2007-01-30

Applicant: Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

Inventor： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

IPC: G05F1/10

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C16/04 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/077 ,  H03K3/356113

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Abstract translation: 在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。 用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。 用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。