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    Semiconductor device and manufacturing method thereof
    1.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5519243A

    公开(公告)日：1996-05-21

    申请号：US305524

    申请日：1994-09-13

    Applicant: Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    Inventor： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L29/76 ,  H01L21/265

    CPC classification number: H01L27/105 ,  Y10S438/901

    Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

    Abstract translation: 根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。 结果，在半导体衬底中形成电容元件。 可以使半导体器件小型化，并提高元件之间的连接的可靠性。

    Semiconductor memory device permitting high speed data transfer and high density integration
    4.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC classification number: G11C11/4096 ,  G11C7/10

    Abstract: In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    Abstract translation: 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Semiconductor memory device carrying out input and output of data in a predetermined bit organization
    5.
    发明授权
    Semiconductor memory device carrying out input and output of data in a predetermined bit organization 失效
    在预定位组织中执行数据的输入和输出的半导体存储器件

    公开(公告)号：US5537351A

    公开(公告)日：1996-07-16

    申请号：US301754

    申请日：1994-09-07

    Applicant: Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    Inventor： Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    IPC: G11C11/401 ,  G11C7/10 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/48 ,  G11C8/00

    CPC classification number: G11C29/48 ,  G11C29/28 ,  G11C7/1006

    Abstract: In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit organization select signal to select data according to a predetermined bit configuration. The selected data is provided to a data bus. In a test mode, the selector unit responds to a test mode signal to provide a test result to a data bus corresponding to a predetermined bit organization. Therefore, only the required data bus is used according to the bit organization and the test mode.

    Abstract translation: 在一般的读出操作中，从存储单元阵列读出的数据由前置放大器组放大。 放大数据被提供给选择器单元。 选择器单元响应位组织选择信号以根据预定位配置选择数据。 所选择的数据被提供给数据总线。 在测试模式中，选择器单元响应于测试模式信号，以向与预定位组织相对应的数据总线提供测试结果。 因此，仅根据位组织和测试模式使用所需的数据总线。

    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode
    6.
    发明授权
    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode 有权
    具有以正常模式提供过驱动电压并在刷新模式下被提供降压电压的读出放大器的半导体器件

    公开(公告)号：US08300480B2

    公开(公告)日：2012-10-30

    申请号：US12897399

    申请日：2010-10-04

    Applicant: Kiyohiro Furutani

    Inventor： Kiyohiro Furutani

    IPC: G11C7/08

    CPC classification number: G11C11/4074 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4068

    Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.

    Abstract translation: 具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于 外部电源电压和降压电路将外部电源电压降低到第二电压。 为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。 在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

    Semiconductor device with refresh control circuit
    7.
    发明申请
    Semiconductor device with refresh control circuit 失效
    具有刷新控制电路的半导体器件

    公开(公告)号：US20100157713A1

    公开(公告)日：2010-06-24

    申请号：US12654109

    申请日：2009-12-10

    Applicant: Kiyohiro Furutani

    Inventor： Kiyohiro Furutani

    IPC: G11C7/00 ,  G11C5/14

    CPC classification number: G11C11/406 ,  G11C8/06 ,  G11C8/08 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4067

    Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

    Abstract translation: 在包括具有待机状态和活动状态的电流降低电路的基于行的控制电路的半导体器件中，刷新控制电路在自刷新模式下以预定的时间间隔生成刷新请求信号，并且时间顺序地产生 与刷新请求信号一次的N次内部有效信号。 基于行的控制电路基于N次内部有效信号时间顺序刷新存储单元的信息。 刷新控制电路通过使电流还原电路处于待机状态来使基于行的控制电路失活。

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