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    Semiconductor device and manufacturing method thereof
    1.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5519243A

    公开(公告)日：1996-05-21

    申请号：US305524

    申请日：1994-09-13

    Applicant: Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    Inventor： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L29/76 ,  H01L21/265

    CPC classification number: H01L27/105 ,  Y10S438/901

    Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

    Abstract translation: 根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。 结果，在半导体衬底中形成电容元件。 可以使半导体器件小型化，并提高元件之间的连接的可靠性。

    Redundancy circuit for repairing defective bits in semiconductor memory device
    3.
    发明授权
    Redundancy circuit for repairing defective bits in semiconductor memory device 失效
    用于修复半导体存储器件中的有缺陷的位的冗余电路

    公开(公告)号：US5574729A

    公开(公告)日：1996-11-12

    申请号：US338817

    申请日：1994-11-10

    Applicant: Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    Inventor： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

    CPC classification number: G11C29/848

    Abstract: A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

    Abstract translation: 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

    Semiconductor device having no through current flow in standby period
    4.
    发明授权
    Semiconductor device having no through current flow in standby period 失效
    半导体器件在待机期间没有通过电流流动

    公开(公告)号：US5321654A

    公开(公告)日：1994-06-14

    申请号：US863975

    申请日：1992-04-06

    Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    IPC: G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

    CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C8/18

    Abstract: A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

    Abstract translation: 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

    Semiconductor memory device comprising a test circuit and a method of operation thereof
    5.
    发明授权
    Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
    半导体存储器件，包括测试电路及其操作方法

    公开(公告)号：US5384784A

    公开(公告)日：1995-01-24

    申请号：US750040

    申请日：1991-08-27

    Applicant: Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    Inventor： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    IPC: G11C11/409 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G06F15/20

    CPC classification number: G11C29/34

    Abstract: A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

    Abstract translation: 半导体存储器件包括存储器阵列。 存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。 第一放大器连接到每个位线对。 对应于第一组，写总线读总线和读/测电路。 对应于第二组，写总线读总线和读/测电路。 列解码器在测试时同时选择多个位线对。 在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

    Semiconductor memory device carrying out input and output of data in a predetermined bit organization
    6.
    发明授权
    Semiconductor memory device carrying out input and output of data in a predetermined bit organization 失效
    在预定位组织中执行数据的输入和输出的半导体存储器件

    公开(公告)号：US5537351A

    公开(公告)日：1996-07-16

    申请号：US301754

    申请日：1994-09-07

    Applicant: Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    Inventor： Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    IPC: G11C11/401 ,  G11C7/10 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/48 ,  G11C8/00

    CPC classification number: G11C29/48 ,  G11C29/28 ,  G11C7/1006

    Abstract: In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit organization select signal to select data according to a predetermined bit configuration. The selected data is provided to a data bus. In a test mode, the selector unit responds to a test mode signal to provide a test result to a data bus corresponding to a predetermined bit organization. Therefore, only the required data bus is used according to the bit organization and the test mode.

    Abstract translation: 在一般的读出操作中，从存储单元阵列读出的数据由前置放大器组放大。 放大数据被提供给选择器单元。 选择器单元响应位组织选择信号以根据预定位配置选择数据。 所选择的数据被提供给数据总线。 在测试模式中，选择器单元响应于测试模式信号，以向与预定位组织相对应的数据总线提供测试结果。 因此，仅根据位组织和测试模式使用所需的数据总线。

    Dynamic random access memory with isolated well structure
    9.
    再颁专利
    Dynamic random access memory with isolated well structure 失效
    具有隔离井结构的动态随机存取存储器

    公开(公告)号：USRE35613E

    公开(公告)日：1997-09-23

    申请号：US496569

    申请日：1995-06-29

    Applicant: Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

    Inventor： Kenichi Yasuda ,  Makoto Suwa ,  Shigeru Mori

    IPC: H01L27/02 ,  H01L27/105 ,  H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/0218 ,  H01L27/105

    Abstract: A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

    Abstract translation: 半导体存储器件包括第一导电类型的半导体衬底中的第一导电类型的阱，该第一导电类型的半导体衬底由第二导电类型阱围绕，存储单元和布置在第一导电类型阱上的外部输入电路之一，另一个位于第二导电类型 类型很好。 对第二导电类型阱施加预定的电源电压，并且将第一导电类型阱连接到地。 在该结构中，从外部输入电路注入的电荷载流子被吸收在第二导电型阱中。 结果，防止电荷载体到达存储单元并破坏其中存储的数据。 因此，可以使晶体管小型化并提高动态随机存取存储器件的集成密度，而不会使源极降低介电强度。

    Green vegetable purees, process for producing the same and foods containing the purees
    10.
    发明授权
    Green vegetable purees, process for producing the same and foods containing the purees 有权
    绿色蔬菜泥，生产过程和含有泥的食物

    公开(公告)号：US06833148B1

    公开(公告)日：2004-12-21

    申请号：US09807731

    申请日：2001-04-16

    Applicant: Keiko Yamamoto ,  Makoto Suwa

    Inventor： Keiko Yamamoto ,  Makoto Suwa

    IPC: A23L1212

    CPC classification number: A23L2/02 ,  A23L19/09

    Abstract: The green vegetable puree production process according to the present invention, which contains a grinding step and an acid addition step and does not include a heating step, produces an unheated green vegetable puree having no catalase activity, containing an acid or acids and having a pH of 2.7 to 4.1. The puree sufficiently maintains the original flavor and taste and freshness of vegetables and is suitable for use in the preparation of foods, especially for vegetable juices.

    Abstract translation: 根据本发明的绿色蔬菜泥生产方法，其包含研磨步骤和酸添加步骤，并且不包括加热步骤，产生不含过氧化氢酶活性的未加热的绿色蔬菜泥，其含有酸或酸并具有pH 为2.7至4.1。 泥浆充分保持蔬菜的原始味道和新鲜度，适合用于制备食品，特别是蔬菜汁。

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