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    Semiconductor device and manufacturing method thereof
    1.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5519243A

    公开(公告)日：1996-05-21

    申请号：US305524

    申请日：1994-09-13

    Applicant: Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    Inventor： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L29/76 ,  H01L21/265

    CPC classification number: H01L27/105 ,  Y10S438/901

    Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

    Abstract translation: 根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。 结果，在半导体衬底中形成电容元件。 可以使半导体器件小型化，并提高元件之间的连接的可靠性。

    Semiconductor memory device permitting high speed data transfer and high density integration
    4.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC classification number: G11C11/4096 ,  G11C7/10

    Abstract: In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    Abstract translation: 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Semiconductor device having no through current flow in standby period
    5.
    发明授权
    Semiconductor device having no through current flow in standby period 失效
    半导体器件在待机期间没有通过电流流动

    公开(公告)号：US5321654A

    公开(公告)日：1994-06-14

    申请号：US863975

    申请日：1992-04-06

    Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    IPC: G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

    CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C8/18

    Abstract: A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

    Abstract translation: 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

    Semiconductor memory device comprising a test circuit and a method of operation thereof
    7.
    发明授权
    Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
    半导体存储器件，包括测试电路及其操作方法

    公开(公告)号：US5384784A

    公开(公告)日：1995-01-24

    申请号：US750040

    申请日：1991-08-27

    Applicant: Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    Inventor： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    IPC: G11C11/409 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G06F15/20

    CPC classification number: G11C29/34

    Abstract: A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

    Abstract translation: 半导体存储器件包括存储器阵列。 存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。 第一放大器连接到每个位线对。 对应于第一组，写总线读总线和读/测电路。 对应于第二组，写总线读总线和读/测电路。 列解码器在测试时同时选择多个位线对。 在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

    Redundancy circuit for repairing defective bits in semiconductor memory device
    8.
    发明授权
    Redundancy circuit for repairing defective bits in semiconductor memory device 失效
    用于修复半导体存储器件中的有缺陷的位的冗余电路

    公开(公告)号：US5574729A

    公开(公告)日：1996-11-12

    申请号：US338817

    申请日：1994-11-10

    Applicant: Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    Inventor： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

    CPC classification number: G11C29/848

    Abstract: A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

    Abstract translation: 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

    Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode
    10.
    发明授权
    Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode 失效
    具有快速数据写入模式的半导体存储器件和以快速数据写入模式写入测试数据的方法

    公开(公告)号：US5903575A

    公开(公告)日：1999-05-11

    申请号：US158837

    申请日：1993-11-29

    Applicant: Shigeru Kikuda

    Inventor： Shigeru Kikuda

    IPC: G11C29/00 ,  G01R31/28 ,  G11C11/401 ,  G11C29/10 ,  G11C29/24 ,  G11C29/34 ,  H01L27/10

    CPC classification number: G11C29/24

    Abstract: Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.

    Abstract translation: 公开了一种包括正常存储器阵列和能够进行相互数据传输的初步存储器阵列的半导体存储器件。 正常存储器阵列中的字线和初步存储器阵列中的字线由单独的行解码器和单独的字驱动器控制。 位线和读出放大器通常提供给正常存储器阵列和初步存储器阵列。 当以预定图案将测试数据写入正常存储器阵列中时，预备存储器阵列中的每个存储单元预先写入与预定图案对应的数据。 然后，在初步存储器阵列的行解码器和字驱动器被使能以使得初步存储器阵列中的字线被激活之后，启用用于正常存储器阵列的行解码器和字驱动器，使得初步存储器阵列中的字线 存储器阵列被激活。 因此，从正常存储器阵列中的一行的存储单元读取的数据信号经由位线被读出放大器同时放大，然后经由位线被传送到预备存储器阵列中的一行的存储单元。 在该结果中，将测试数据一次写入正常存储器阵列中的一行的存储单元。

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