Semiconductor memory device that can read out data at high speed
    2.
    发明授权
    Semiconductor memory device that can read out data at high speed 失效
    可高速读出数据的半导体存储器件

    公开(公告)号:US5600607A

    公开(公告)日:1997-02-04

    申请号:US435691

    申请日:1995-05-05

    CPC classification number: G11C11/4093 G11C11/4076 G11C11/4096 G11C7/22

    Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

    Abstract translation: phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号,使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。 列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号,以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。 差分放大器响应于差分放大器激活信号,用于放大从数据输入和输出线施加的数据,以通过读出数据线将其提供给选择器。

    Semiconductor memory device permitting high speed data transfer and high
density integration
    3.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号:US5586076A

    公开(公告)日:1996-12-17

    申请号:US304899

    申请日:1994-09-13

    CPC classification number: G11C11/4096 G11C7/10

    Abstract: In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    Abstract translation: 在存储单元阵列中,数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置,以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此,减少了子数据线的长度,这降低了浮动电容,可以高速地执行读和写操作,并且可以选择性地操作子数据线。 此外,可以减少对子数据线进行充电所需的功率,并且可以减小半导体存储器件的整体功耗。

    Semiconductor memory device that can read out data at high speed
    4.
    发明授权
    Semiconductor memory device that can read out data at high speed 失效
    可高速读出数据的半导体存储器件

    公开(公告)号:US5907509A

    公开(公告)日:1999-05-25

    申请号:US978421

    申请日:1997-11-25

    CPC classification number: G11C11/4093 G11C11/4076 G11C11/4096 G11C7/22

    Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

    Abstract translation: phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号,使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。 列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号,以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。 差分放大器响应于差分放大器激活信号,用于放大从数据输入和输出线施加的数据,以通过读出数据线将其提供给选择器。

    Fuel injection amount control system and fuel injection amount control device for multi-cylinder internal combustion engine
    10.
    发明授权
    Fuel injection amount control system and fuel injection amount control device for multi-cylinder internal combustion engine 有权
    燃油喷射量控制系统和多缸内燃机燃油喷射量控制装置

    公开(公告)号:US08833348B2

    公开(公告)日:2014-09-16

    申请号:US13194923

    申请日:2011-07-30

    Abstract: A fuel injection amount control system acquires a pre-correction air-fuel ratio imbalance index value that increases as the degree of ununiformity in the air-fuel ratio among cylinders increases, based on an output value of an upstream air-fuel ratio sensor, and obtains a value (intake air amount correlation value) corresponding to the intake air amount and a value (engine speed correlation value) corresponding to the engine speed over a period in which the pre-correction air-fuel ratio imbalance index value is acquired. Also, a post-correction air-fuel ratio imbalance index value is acquired by correcting the pre-correction air-fuel ratio imbalance index value based on the intake air amount correlation value and the engine speed correlation value, and the air-fuel ratio of the engine is controlled based on the post-correction air-fuel ratio imbalance index value.

    Abstract translation: 燃料喷射量控制系统获取基于上游空燃比传感器的输出值随着气缸中的空燃比的不均匀度增加而增加的预校正空燃比不平衡指数值,以及 获取与获取预校正空燃比不平衡指数值的期间对应的与进气量对应的值(进气量相关值)和与发动机转速对应的值(发动机转速相关值)。 此外,通过基于进气量相关值和发动机转速相关值校正预校正空燃比不平衡指数值来获取校正后空燃比不平衡指数值,并且, 基于校正后的空燃比不平衡指数值来控制发动机。

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