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    Semiconductor memory device that can read out data at high speed
    5.
    发明授权
    Semiconductor memory device that can read out data at high speed 失效
    可高速读出数据的半导体存储器件

    公开(公告)号：US5600607A

    公开(公告)日：1997-02-04

    申请号：US435691

    申请日：1995-05-05

    Applicant: Kiyohiro Furutani ,  Hiroshi Miyamoto

    Inventor： Kiyohiro Furutani ,  Hiroshi Miyamoto

    IPC: G11C11/401 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C8/00

    CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/22

    Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

    Abstract translation: phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。 列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。 差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

    Semiconductor memory device permitting high speed data transfer and high density integration
    6.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    Applicant: Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    Inventor： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC classification number: G11C11/4096 ,  G11C7/10

    Abstract: In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    Abstract translation: 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Semiconductor memory device that can read out data at high speed
    7.
    发明授权
    Semiconductor memory device that can read out data at high speed 失效
    可高速读出数据的半导体存储器件

    公开(公告)号：US5907509A

    公开(公告)日：1999-05-25

    申请号：US978421

    申请日：1997-11-25

    Applicant: Kiyohiro Furutani ,  Hiroshi Miyamoto

    Inventor： Kiyohiro Furutani ,  Hiroshi Miyamoto

    IPC: G11C11/401 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/00

    CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/22

    Abstract: A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

    Abstract translation: phi C生成电路向列地址缓冲器提供列地址缓冲器控制信号，使得列地址缓冲器在差分放大器的操作周期期间保持锁存操作。 列地址缓冲器响应列地址缓冲器控制信号以锁存输入地址信号，以向列D和PAE生成电路提供列地址信号。 phi D和PAE生成电路根据列地址信号和列访问激活信号向差分放大器提供差分放大器激活信号。 差分放大器响应于差分放大器激活信号，用于放大从数据输入和输出线施加的数据，以通过读出数据线将其提供给选择器。

    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode
    10.
    发明授权
    Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode 有权
    具有以正常模式提供过驱动电压并在刷新模式下被提供降压电压的读出放大器的半导体器件

    公开(公告)号：US08300480B2

    公开(公告)日：2012-10-30

    申请号：US12897399

    申请日：2010-10-04

    Applicant: Kiyohiro Furutani

    Inventor： Kiyohiro Furutani

    IPC: G11C7/08

    CPC classification number: G11C11/4074 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4068

    Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.

    Abstract translation: 具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于 外部电源电压和降压电路将外部电源电压降低到第二电压。 为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。 在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

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