公开(公告)号：US20170125593A1

公开(公告)日：2017-05-04

申请号：US14925680

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US20170110582A1

公开(公告)日：2017-04-20

申请号：US14887873

申请日：2015-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.

公开(公告)号：US20170040439A1

公开(公告)日：2017-02-09

申请号：US15298462

申请日：2016-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract translation: 提供半导体结构及其形成方法。 该半导体结构包括在基板上形成的基板和翅片结构。 半导体结构还包括形成在翅片结构周围的隔离结构和横跨翅片结构形成的栅极结构。 此外，栅极结构包括形成在鳍状结构上的第一部分和形成在隔离结构上的第二部分，并且栅极结构的第二部分包括延伸到隔离结构中的延伸部分。

公开(公告)号：US20160372378A1

公开(公告)日：2016-12-22

申请号：US15253805

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US20160365446A1

公开(公告)日：2016-12-15

申请号：US14792303

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/283

CPC classification number: H01L29/7845 ,  H01L21/28008 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

Abstract translation: 提供了一种FinFET器件结构及其形成方法。 FinFET器件结构包括形成在衬底上的阻挡层和形成在阻挡层上的翅片结构。 FinFET器件结构包括形成在鳍结构上的栅极结构和与栅极结构相邻的源极/漏极（S / D）结构。 S / D结构的底面位于比止挡层的底面高或者与其平齐的位置。

公开(公告)号：US20160365275A1

公开(公告)日：2016-12-15

申请号：US14799258

申请日：2015-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/785

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括形成在衬底上的第一金属层和形成在第一金属层上的互连结构。 互连结构包括上部，中部和下部，中间部分连接在上部和下部之间。 上部和下部各自具有恒定的宽度，并且中间部分具有从上部到下部逐渐变细的锥形宽度。

公开(公告)号：US20160240537A1

公开(公告)日：2016-08-18

申请号：US14698831

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat portion.

Abstract translation: 半导体器件包括Fin FET晶体管。 鳍式FET晶体管包括沿第一方向延伸的第一鳍状结构，栅极堆叠以及源极和漏极。 栅堆叠包括栅极电极层和栅极电介质层，覆盖翅片结构的一部分并且沿垂直于第一方向的第二方向延伸。 源极和漏极中的每一个包括设置在鳍结构上的应力层。 应力层对栅叠层下的鳍结构的沟道层施加应力。 应力层穿过栅极叠层。 在垂直于第一和第二方向的第三方向上的应力层和翅片结构之间的垂直界面包括平坦部分。