公开(公告)号：US10510657B2

公开(公告)日：2019-12-17

申请号：US15715327

申请日：2017-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522

摘要： A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.

公开(公告)号：US09721894B2

公开(公告)日：2017-08-01

申请号：US15361699

申请日：2016-11-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Kang Fu ,  Hsien-Chang Wu ,  Li-Lin Su ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321

CPC分类号： H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

摘要： In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US09219033B2

公开(公告)日：2015-12-22

申请号：US14221509

申请日：2014-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/00 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L21/288

CPC分类号： H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

摘要翻译： 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US20150270215A1

公开(公告)日：2015-09-24

申请号：US14221509

申请日：2014-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/288 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

摘要翻译： 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US20240258166A1

公开(公告)日：2024-08-01

申请号：US18608673

申请日：2024-03-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

摘要： Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US20240213157A1

公开(公告)日：2024-06-27

申请号：US18600197

申请日：2024-03-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/324 ,  H01L21/76876 ,  H01L23/5226

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US12009202B2

公开(公告)日：2024-06-11

申请号：US17379161

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

摘要： A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20240085803A1

公开(公告)日：2024-03-14

申请号：US18514254

申请日：2023-11-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC分类号： G03F7/00 ,  G03F7/004 ,  G03F7/09 ,  H01L21/768

CPC分类号： G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

摘要： Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11710700B2

公开(公告)日：2023-07-25

申请号：US17391216

申请日：2021-08-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

摘要： A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US11640924B2

公开(公告)日：2023-05-02

申请号：US17314877

申请日：2021-05-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Yu-Chieh Liao ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3105

摘要： The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.