A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.