公开(公告)号：US20240172454A1

公开(公告)日：2024-05-23

申请号：US18057836

申请日：2022-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Heng Wu ,  Min Gyu Sung ,  Chanro Park

IPC: H10B61/00 ,  H03K19/173 ,  H03K19/20 ,  H10B53/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L27/228 ,  H01L27/11502 ,  H01L27/2454 ,  H01L45/04 ,  H03K19/1733 ,  H03K19/20

Abstract: Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

公开(公告)号：US20240155826A1

公开(公告)日：2024-05-09

申请号：US17983014

申请日：2022-11-08

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Julien Frougier ,  Ruilong Xie ,  Chanro Park

IPC: H01L23/48

CPC classification number: H01L27/10811 ,  H01L23/481 ,  H01L27/10826

Abstract: A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.

公开(公告)号：US20240153990A1

公开(公告)日：2024-05-09

申请号：US18053795

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Juntao Li

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/481 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.

公开(公告)号：US20240145584A1

公开(公告)日：2024-05-02

申请号：US18051504

申请日：2022-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Kangguo Cheng ,  Ruilong Xie ,  Chanro Park ,  Andrew Gaul ,  Min Gyu Sung

IPC: H01L29/66

CPC classification number: H01L29/66984

Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

公开(公告)号：US20240145578A1

公开(公告)日：2024-05-02

申请号：US18050560

申请日：2022-10-28

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Ruilong Xie ,  Shogo Mochizuki ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.

公开(公告)号：US20240145539A1

公开(公告)日：2024-05-02

申请号：US18051958

申请日：2022-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Kangguo Cheng ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure including a stacked transistor structure comprising a top device stacked directly above a bottom device, and a bilayer gate dielectric layer separating the top device from the bottom device.

公开(公告)号：US20240128345A1

公开(公告)日：2024-04-18

申请号：US17964115

申请日：2022-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Julien Frougier

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823871 ,  H01L29/78696

Abstract: A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

公开(公告)号：US20240128333A1

公开(公告)日：2024-04-18

申请号：US17967428

申请日：2022-10-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Chen Zhang ,  Min Gyu Sung ,  Heng Wu

IPC: H01L29/417 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/76283 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L23/5286

Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

公开(公告)号：US20240128318A1

公开(公告)日：2024-04-18

申请号：US17967016

申请日：2022-10-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Kangguo Cheng ,  Julien Frougier

IPC: H01L29/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

公开(公告)号：US20240113117A1

公开(公告)日：2024-04-04

申请号：US17936416

申请日：2022-09-29

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Julien Frougier ,  Kangguo Cheng ,  Ruilong Xie ,  Chanro Park

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.