公开(公告)号：US3748543A

公开(公告)日：1973-07-24

申请号：US3748543D

申请日：1971-04-01

Applicant: MOTOROLA INC

Inventor： ROBERSON D

IPC: H01L23/057 ,  H01L23/10 ,  H01L23/535 ,  H01L5/02

CPC classification number: H01L23/10 ,  H01L23/057 ,  H01L23/535 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: There is disclosed a hermetically sealed semiconductor package which is physically thin, allowing mounting within apertures formed in printed circuit boards which are stacked one on top of another in a high density configuration. The hermetic seal is made to a planar surface resulting in high reliability devices in which the leads to the interior of the package are made through ''''cross under'''' regions which are provided with planar top surfaces. The ''''cross under'''' region is a region of extremely low resistivity, high temperature material. Because this material is utilized as part of the lead to the device and because the hermetic seal is made on top of the ''''cross under,'''' higher temperatures, which would ordinarily destroy metal leads, can be applied to the sealing material both on top of the ''''cross unders'''' and on top of the substrate for increasing the reliability of the seal. This package replaces the more fragile prior art hermetically sealed devices which include a number of piece parts. A device packaged in the subject manner is also used as a hermetically sealed substitute for beam lead devices, since the subject devices are thin, have a higher reliability than unsealed beam lead devices and are impervious to welding and other contaminants during mounting.

Abstract translation: 公开了一种物理上薄的密封半导体封装，允许安装在以高密度配置堆叠在另一个之上的印刷电路板中形成的孔内。 气密密封件制成平面表面，导致高可靠性的装置，其中通过设置有平坦顶表面的“交叉”的区域制造通向包装内部的引线。 “交叉”区域是极低电阻率，高温材料的区域。 因为这种材料被用作引导装置的一部分，并且由于气密密封是在“交叉下方”的顶部制成的，因此通常会破坏金属引线的较高温度可以施加到密封材料上 “交叉下”和衬底顶部，以提高密封的可靠性。

公开(公告)号：US3706915A

公开(公告)日：1972-12-19

申请号：US3706915D

申请日：1970-03-09

Applicant: GEN ELECTRIC

Inventor： LOOTENS WILLIAM F ,  FLOWERS JOSEPH K

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L23/492 ,  H01L29/00 ,  H01L5/02

CPC classification number: H01L24/33 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/492 ,  H01L24/32 ,  H01L24/83 ,  H01L29/00 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00011 ,  H01L2924/00012

Abstract: A semiconductor device is formed by scoring a conductive surface of a substrate and locating a semiconductive element over a portion of the capillary formed by scoring. Solder in molten form is associated with the portion of the capillary remote from the semiconductive element and is drawn by the capillary under the semiconductive element to form a tenacious, low impedance interconnection therewith. The substrate may be a dielectric or a metal heat sink. Leads may be secured to the substrate similarly as the semiconductive element is secured. A dielectric substrate may be similarly secured to a metal heat sink. Multiple interconnecting or parallel capillaries may be employed. The capillaries may be provided with a remote interconnection, an interconnection for solder receipt, or an indicator portion remote from solder receipt. Plural semiconductive elements may be mounted to a single substrate with solder fed to the semiconductive elements simultaneously or sequentially. On a dielectric substrate the semiconductive elements may be electrically isolated by removing a conductive surface portion after soldering. The capillaries may also take the form of apertures.

Abstract translation: 通过刻划基板的导电表面并将半导体元件定位在通过刻痕形成的毛细管的一部分上而形成半导体器件。 熔融形式的焊料与远离半导体元件的毛细管部分相关联，并由半导体元件下方的毛细管牵引，以形成与之紧密的低阻抗互连。 衬底可以是电介质或金属散热器。 类似于半导体元件被固定，引线可以固定到基底上。 电介质基板可以类似地固定到金属散热器。 可以采用多个互连或平行毛细管。 毛细管可以设置有远程互连，用于焊料接收的互连或远离焊料接收的指示器部分。 多个半导体元件可以被安装到单个基板上，同时或顺序地将焊料馈送到半导体元件。 在电介质基板上，半导体元件可以通过在焊接之后去除导电表面部分而被电隔离。 毛细管也可以采取孔径的形式。

公开(公告)号：US3660733A

公开(公告)日：1972-05-02

申请号：US3660733D

申请日：1969-10-29

Applicant: FERNANDO ZHOZEVICH VILF ,  ALEXANDR PAVLOVICH LYSENKO

Inventor： VILF FERNANDO ZHOZEVICH ,  LYSENKO ALEXANDR PAVLOVICH

IPC: H01L23/488 ,  H01L45/00 ,  H01L5/02

CPC classification number: H01L23/488 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L47/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising a homogeneous semiconductor crystal and two antibarrier contacts, the area of one of which is smaller than that of the other and the diameter is smaller than the distance between the contacts and is limited in absolute value lying within 1 to 100 microns. This device can perform various functions, such as an oscillator, or a currector or a switch.

Abstract translation: 一种包括均匀半导体晶体和两个抗阻抗触点的半导体器件，其中一个的面积小于另一个的面积，其直径小于触点之间的距离，并且绝对值的限制在1至100微米之内。 该装置可以执行各种功能，例如振荡器或编曲器或开关。

公开(公告)号：US3657610A

公开(公告)日：1972-04-18

申请号：US3657610D

申请日：1970-06-24

Applicant: NIPPON ELECTRIC CO

Inventor： YAMAMOTO HIROHIKO ,  SHIRAISHI MASAMICHI

IPC: H05K1/18 ,  H01L21/60 ,  H01L23/10 ,  H01L23/485 ,  H05K1/16 ,  H01L5/02

CPC classification number: H01L24/10 ,  H01L23/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In a self-sealing semiconductor device of the face-down bonding type, a plurality of electrode bumps are formed on one surface of semiconductor substrate and surrounded by a sealing projection of substantially uniform height.

Abstract translation: 在面向下接合型的自密封半导体器件中，在半导体衬底的一个表面上形成多个电极凸块，并被基本均匀的高度的密封突起包围。

公开(公告)号：US3652904A

公开(公告)日：1972-03-28

申请号：US3652904D

申请日：1970-03-31

Applicant: HITACHI LTD

Inventor： TAKAHASHI KAZUSABURO ,  SASAKI TAKESHI ,  TAKEUCHI HISAUKE ,  MORITA KEIICHI ,  TODA TADATOSHI

IPC: H01L21/52 ,  H01L23/04 ,  H01L23/051 ,  H01L23/40 ,  H01L23/48 ,  H01L5/02

CPC classification number: H01L23/4006 ,  H01L23/051 ,  H01L24/72 ,  H01L2023/4025 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12036 ,  H01L2924/00

Abstract: A semiconductor device comprising a semiconductor wafer, a base electrode soldered to one face of the wafer, a first conductive block secured to the base electrode, a second conductive block being in slidable contact with the other face of the wafer, an annular insulator soldered to the first conductive block, a flexible sheet being so secured to the annular insulator as to seal the wafer off from the atmosphere, and means for compressing the conductive blocks to the wafer, characterized in that a hard and thin metallic film is formed on the surface of the second conductive block, whereby a sticking caused between the second conductive block and the wafer can be prevented.

Abstract translation: 一种半导体器件，包括半导体晶片，焊接到所述晶片的一个面的基极，固定到所述基极的第一导电块，与所述晶片的另一面可滑动接触的第二导电块，焊接到 第一导电块，柔性片被固定到环形绝缘体以将晶片与大气隔绝，以及用于将导电块压缩到晶片的装置，其特征在于，在表面上形成硬且薄的金属膜 的第二导电块，从而可以防止在第二导电块和晶片之间产生的粘附。

公开(公告)号：US3622844A

公开(公告)日：1971-11-23

申请号：US3622844D

申请日：1969-08-18

Applicant: TEXAS INSTRUMENTS INC

Inventor： BARELLI ANTHONY E ,  SHAUNFIELD WALLACE N JR

IPC: H01L21/00 ,  H01L23/482 ,  H01L31/00 ,  H01L31/107 ,  H01L9/00 ,  H01L5/02 ,  H01L15/00

CPC classification number: H01L31/107 ,  H01L21/00 ,  H01L23/482 ,  H01L31/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An avalanche Schottky-barrier photodiode includes a symmetrical metallic grid network deposited over a semiconductor substrate and surrounded by one or more metallic guard rings. When a sufficiently high voltage bias is supplied to the metallic grid network, carriers generated by light impinging upon the semiconductor substrate through the grid network are multiplied by the avalanche gain operation of the photodiode.

公开(公告)号：US3619738A

公开(公告)日：1971-11-09

申请号：US3619738D

申请日：1970-10-12

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： OTSUKA MICHIO

IPC: H01L23/482 ,  H01L29/00 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/744 ,  H01L5/02

CPC classification number: H01L29/744 ,  H01L23/4824 ,  H01L29/00 ,  H01L29/0813 ,  H01L29/102 ,  H01L29/41708 ,  H01L29/41716 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor device with a control grid and comprising at least three semiconductor layers of alternately different conductivity types, portions of the second layer are protruded through the first layer to be exposed on the surface of the first layer, second electrode is mounted on the exposed portions in ohmic contact therewith, a third electrode is mounted to insulating cover the second electrode and the exposed portions containing the same, and the third electrode is in ohmic contact with the first layer.

公开(公告)号：US3611072A

公开(公告)日：1971-10-05

申请号：US3611072D

申请日：1969-08-27

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： HAMILTON DONALD R

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/74 ,  H01L29/744 ,  H01L5/02 ,  H01L9/12 ,  H01L11/10

CPC classification number: H01L29/0839 ,  H01L29/41716 ,  H01L29/744

Abstract: A gate controlled switch has a plurality of cathode regions distributed throughout but electrically isolated from the gate region of the switch. Each cathode region has an integral resistive portion which enables the region to control the last current flow which occurs when the switch is turned off so that each cathode region has two distinct separate regions integral with each other, and each having its own individual function. During normal operation of the switch, substantially all of the forward current flows through essentially all of the cathode except for the integral resistive portion of the region. During turnoff of the switch the last current to flow in the switch is caused to flow through the integral resistive element portion of the cathode region.

公开(公告)号：US3581387A

公开(公告)日：1971-06-01

申请号：US3581387D

申请日：1967-11-29

Applicant: GEN MOTORS CORP

Inventor： BUCK ROBERT E ,  RITTMANN ALBERT D ,  SAYERS EUGENE H ,  METZGER ROBERT W JR

IPC: H01L23/495 ,  B01J17/00 ,  H01L1/14 ,  H01L5/02

CPC classification number: H01L23/49568 ,  H01L23/49562 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/1301 ,  Y10T29/49172 ,  Y10T29/49829 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MAKING IT. A SEMICONDUCTIVE ELEMENT IS MOUNTED ON A FLAT STRIP. A PORTION OF THE STRIP IS PARTIALLY SEPARATED FROM, AND RAISED ABOVE THE PLANE OF, THE STRIP. THE RAISED PORTION IS EVENTUALLY COMPLETELY SEPARATED FROM THE STRIP, AND FORMS A TERMINAL MEMBER FOR THE SEMICONDUCTIVE ELEMENT. THE ELEMENT AND CONNECTION TO THE TERMINAL ARE ENCLOSED, PREFERABLY IN A PLASTIC POTTING. MEANS ARE PROVIDED TO INCREASE THE RIGIDITY OF THE STRIP IN THE ENCLOSURE AREA. MEANS ARE ALSO PROVIDED TO ENHANCE ADHESION OF A PLASTIC POTTING TO THE STRIP AND TERMINAL MEMBERS. A PLURALITY OF DEVICES CAN BE SIMULTANEOUSLY OR SUCCESSIVELY FORMED FROM A SINGLE STRIP. MULITPLE TERMINAL DEVICES CAN BE FORMED USING ADJACENT MULTIPLE RAISED PORTIONS ON THE STRIP.

公开(公告)号：US3564354A

公开(公告)日：1971-02-16

申请号：US3564354D

申请日：1968-12-11

Applicant: SIGNETICS CORP

Inventor： AOKI EDWARD MASAMI ,  PETERSON DAVID R

IPC: H01L21/00 ,  H01L23/525 ,  H01L1/14 ,  H01L5/02 ,  H01L19/00

CPC classification number: H01L23/5256 ,  H01L21/00 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/055 ,  Y10T29/49107 ,  Y10T29/49124 ,  H01L2924/00

Abstract: SEMICONDUCTOR STRUCTURE HAVING A FUSIBLE LINK FORMED BY A PORTION IN A LEAD STRUCTURE CARRIED BY A SEMICONDUCTER BODY IN WHICH THE PORTION IS CHARACTERIZED IN THAT IT CAN BE FUSED WITH A RELATIVELY PRECISE CURRENT LEVEL, AND A METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE WITH SUCH A FUSIBLE LINK.