公开(公告)号：US11744022B2

公开(公告)日：2023-08-29

申请号：US17536429

申请日：2021-11-29

申请人： Kyocera AVX Components (San Diego), Inc.

发明人： Seung Hyuk Choi ,  Hyun Jun Hong ,  Tae Wook Kim ,  Cheong Ho Ryu ,  Young Sang Kim ,  Sung Jun Kim

IPC分类号： H05K3/46 ,  H05K3/00 ,  H05K3/18 ,  H05K3/28 ,  H05K3/42

CPC分类号： H05K3/0026 ,  H05K3/0014 ,  H05K3/185 ,  H05K3/188 ,  H05K3/28 ,  H05K3/423 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09018 ,  H05K2201/09118 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/0582 ,  H05K2203/0588 ,  H05K2203/072 ,  H05K2203/107 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of forming a multi-layer circuit on a curved substrate includes forming, by a laser direct structuring process, a first layer of the multi-layer circuit on a first surface of the curved substrate. The method includes applying a first layer of paint to the first layer of the multi-layer circuit. The method includes forming, by the laser direct structuring process, a second layer of the multi-layer circuit on the first layer of the paint and electrically coupled to the first layer of the multi-layer circuit. The method includes applying a second layer of paint over the second layer of the multi-layer circuit and forming, by the laser direct structuring process, a third layer of the multi-layer circuit on the second layer of the paint and electrically coupled to the second layer of the multi-layer circuit.

公开(公告)号：US20170330767A1

公开(公告)日：2017-11-16

申请号：US15586716

申请日：2017-05-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Un-Byoung Kang ,  Tae-Je CHO ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC分类号： H01L21/48 ,  C23C14/58 ,  C23C14/34 ,  C23C14/20 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02 ,  B05D7/00 ,  B05D3/02 ,  B05D1/38 ,  B05D1/32 ,  B05D1/00

CPC分类号： H01L21/4857 ,  B05D1/005 ,  B05D1/32 ,  B05D1/38 ,  B05D3/0209 ,  B05D7/546 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/205 ,  C23C14/34 ,  C23C14/588 ,  C23C18/00 ,  C23C18/38 ,  H01L21/486 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0588 ,  H01L2924/01047 ,  H01L2224/81

摘要： A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US09415469B2

公开(公告)日：2016-08-16

申请号：US14340850

申请日：2014-07-25

申请人： SAN-EI KAGAKU CO., LTD.

发明人： Yasuhiro Takase ,  Kazuki Hanada ,  Kazunori Kitamura

IPC分类号： B23K35/36 ,  H05K1/09 ,  B23K35/02 ,  B23K1/20 ,  B23K1/00 ,  B23K3/06 ,  B23K3/08 ,  H05K3/34

CPC分类号： B23K35/3613 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0638 ,  B23K3/08 ,  B23K35/0222 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/3612 ,  B23K2101/42 ,  H01L2224/11 ,  H05K3/3484 ,  H05K2203/0139 ,  H05K2203/0425 ,  H05K2203/043 ,  H05K2203/0445 ,  H05K2203/0588 ,  H05K2203/0769 ,  H05K2203/0773 ,  H05K2203/111

摘要： The present invention provides a solder bump formation resin composition which ensures resist (e.g., dry film) removability and which exhibits excellent solder bonding performance, even when the working substrate is placed at high temperature during reflowing, baking, or a similar process. The solder bump formation resin composition contains (A) at least one species selected from among an alkali-dissoluble thermoplastic resin having an acid value (mgKOH/g) of 110 or higher, an unsaturated fatty acid polymer having an acid value of 80 or higher, and an unsaturated fatty acid-aliphatic unsaturated compound copolymer having an acid value of 50 or higher; (B) a solvent; and (C) a solder powder, and contains no activating agent.

摘要翻译： 本发明提供了一种焊料凸点形成树脂组合物，其即使在回流，烘烤或类似工艺中将工作基板放置在高温下时也能够确保抗蚀剂（例如干膜）的去除性，并且具有优异的焊接性能。 焊锡凸块形成用树脂组合物含有（A）选自酸值（mgKOH / g）为110以上的碱溶性热塑性树脂中的至少一种，酸值为80以上的不饱和脂肪酸聚合物 ，和酸值为50以上的不饱和脂肪酸 - 脂肪族不饱和化合物共聚物; （B）溶剂; 和（C）焊料粉末，不含活化剂。

公开(公告)号：US20150351229A1

公开(公告)日：2015-12-03

申请号：US14289098

申请日：2014-05-28

申请人： Avago Technologies General IP (Singapore) Pte. Ltd

发明人： Lea-Teng Lee ,  Sarah Haney

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K1/09

CPC分类号： H05K1/0268 ,  H05K2201/09881 ,  H05K2201/09909 ,  H05K2203/0353 ,  H05K2203/0588

摘要： A printed circuit board (PCB) comprises a non-conductive base layer, a conductive interconnect disposed on the non-conductive base layer and comprising at least two surface pads separated by a trench, and a insulating dam disposed in the trench, wherein the insulating dam electrically isolates the at least two surface pads and has an upper surface that is substantially co-planar with respective upper surfaces of the at least two surface pads.

摘要翻译： 印刷电路板（PCB）包括非导电基底层，布置在非导电基底层上的导电互连，并且包括由沟槽分隔开的至少两个表面焊盘和设置在沟槽中的绝缘堤坝，其中绝缘 坝至少两个表面焊盘电隔离，并且具有与至少两个表面焊盘的相应上表面基本共面的上表面。

公开(公告)号：US20150177621A1

公开(公告)日：2015-06-25

申请号：US14634527

申请日：2015-02-27

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Jeong Woo LEE ,  Going Sik Kim

IPC分类号： G03F7/30 ,  H05K3/46

CPC分类号： G03F7/30 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/2024 ,  H05K1/0284 ,  H05K3/28 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0588 ,  H05K2203/1476

摘要： Disclosed herein is a printed circuit board, including: a base substrate on which a circuit layer is formed; and multi-layer insulating layers formed in a plurality of layers on the base substrate, including the circuit layer, each of the plurality of layers being formed to have a step structure, wherein the multi-layer insulating layer is formed of heterogeneous materials.

摘要翻译： 这里公开了一种印刷电路板，包括：基底，其上形成有电路层; 以及在所述基底基板上形成为多层的多层绝缘层，所述多层绝缘层包括所述电路层，所述多层中的每一层形成为具有台阶结构，其中所述多层绝缘层由异质材料形成。

公开(公告)号：US20150062915A1

公开(公告)日：2015-03-05

申请号：US14019257

申请日：2013-09-05

申请人： Cree, Inc.

发明人： Christopher P. Hussell ,  Jesse Colin Reiherzer ,  Erin R. F. Welch ,  Florin A. Tudorica

IPC分类号： H01L33/10 ,  F21K99/00 ,  F21V7/22

CPC分类号： F21V7/22 ,  F21K9/60 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/0588 ,  H01L2924/00

摘要： Light emitter devices and methods are provided herein. In some aspects, emitter devices and methods provided herein are for light emitting diode (LED) chips and can include providing a substrate, a conductive trace over the substrate, and at least one or more direct attach LED chip over the substrate. A layer of non-conductive and reflective material is disposed over the surface of wherein the layer of reflective material covers at least 25% or more of a surface of the substrate.

摘要翻译： 本文提供了发光器件和方法。 在一些方面，本文提供的发射器件和方法用于发光二极管（LED）芯片，并且可以包括提供衬底，衬底上的导电迹线以及衬底上的至少一个或多个直接附接LED芯片。 非导电和反射材料层设置在其上的反射材料层覆盖基底表面的至少25％或更多的表面上。

公开(公告)号：US20140092569A1

公开(公告)日：2014-04-03

申请号：US14040358

申请日：2013-09-27

申请人： KYOCERA SLC Technologies Corporation

发明人： Keizou SAKURAI

IPC分类号： H05K1/18

CPC分类号： H05K1/186 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/1461 ,  H05K3/3452 ,  H05K3/4614 ,  H05K3/4697 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2203/0588 ,  H05K2203/061 ,  Y10T29/49126 ,  H01L2924/00

摘要： A wiring board includes a base wiring board 10 and a frame wiring board 20. The base wiring board 10 has an element mounting portion 1a and a frame-shaped frame joining portion 1b on the upper surface and a solder resist layer 4 deposited in a portion between the element mounting portion 1a and the frame joining portion 1b. In the wiring board 10, a first joining pad 6 provided in the frame joining portion 1b and a second joining pad 16 provided in a lower surface of the frame wiring board 20 are joined together via a solder bump H so that a gap may be formed between the frame joining portion 1b and the frame wiring board 20. The base wiring board 10 has a resin injection hole 8 penetrating through the base wiring board 10 in the frame joining portion 1b, and the gap is filled with a sealing resin 18.

摘要翻译： 布线基板包括基底布线板10和框架布线板20.基布线板10具有在上表面上的元件安装部分1a和框架形框架接合部分1b以及沉积在部分上的阻焊层4 在元件安装部分1a和框架接合部分1b之间。 在布线板10中，设置在框架接合部分1b中的第一接合焊盘6和设置在框架接线板20的下表面中的第二接合焊盘16通过焊料凸块H接合在一起，从而可以形成间隙 框架接合部分1b和框架接线板20之间。底部布线板10具有穿过框架接合部分1b中的基底布线板10的树脂注入孔8，并且间隙填充有密封树脂18。

公开(公告)号：US20130264105A1

公开(公告)日：2013-10-10

申请号：US13712385

申请日：2012-12-12

申请人： SAN-EI-KAGAKU CO., LTD.

发明人： Kazunori KITAMURA

IPC分类号： H05K1/02 ,  H05K3/00 ,  H05K1/18

CPC分类号： H05K1/0296 ,  H01L23/49894 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2924/12042 ,  H05K1/181 ,  H05K3/00 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0588 ,  Y02P70/613 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： The present invention provides a solder-mounted board which realizes reliable mounting of a component thereon; a method for producing the board; and a semiconductor device. The solder-mounted board includes a substrate; a wiring layer; a solder pad for mounting a component by the mediation of the solder; and an insulating layer which covers the wiring layer such that at least the solder pad is exposed, the wiring layer, the solder pad, and the insulating layer being provided on at least one surface of the substrate, wherein the insulating layer is formed of a first insulating layer provided on the substrate and the wiring layer, and a second insulating layer provided on at least a portion of the first insulating layer.

摘要翻译： 本发明提供了一种实现可靠地安装组件的焊接安装板， 一种生产该板的方法; 和半导体器件。 焊接安装板包括基板; 布线层; 用于通过焊料中介来安装部件的焊盘; 以及绝缘层，其覆盖所述布线层，使得至少所述焊盘露出，所述布线层，所述焊盘和所述绝缘层设置在所述基板的至少一个表面上，其中所述绝缘层由 设置在所述基板和所述布线层上的第一绝缘层，以及设置在所述第一绝缘层的至少一部分上的第二绝缘层。

公开(公告)号：US20130157200A1

公开(公告)日：2013-06-20

申请号：US13763232

申请日：2013-02-08

申请人： Nitto Denko Corporation

发明人： Yasushi TAMURA ,  Ryouji SUEZAKI ,  Tetsuya OHSAWA ,  Hiroyuki TANABE ,  Hitoki KANAGAWA

IPC分类号： G03F7/20

CPC分类号： G03F7/2022 ,  G03F1/144 ,  G03F1/70 ,  G11B5/4846 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/28 ,  H05K2201/0191 ,  H05K2203/0505 ,  H05K2203/0588 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A suspension board with circuit includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, an insulating cover layer formed on the insulating base layer so as to cover the conductive pattern, and an insertion portion to be inserted into an E-block. A thickness of the insulating cover layer in the insertion portion is larger than a thickness of the insulating cover layer in a portion other than the insertion portion.

摘要翻译： 具有电路的悬挂板包括金属支撑板，形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，形成在绝缘基底层上以覆盖导电图案的绝缘覆盖层， 以及插入到E块中的插入部。 插入部中的绝缘覆盖层的厚度比除了插入部以外的部分的绝缘覆盖层的厚度大。

公开(公告)号：US20120103665A1

公开(公告)日：2012-05-03

申请号：US12915128

申请日：2010-10-29

申请人： Kum Cheong Adam CHAN ,  Chee Yung Tan ,  Chen Chin Jimmy Wong

发明人： Kum Cheong Adam CHAN ,  Chee Yung Tan ,  Chen Chin Jimmy Wong

IPC分类号： H05K1/09 ,  B23K20/24 ,  B23K1/20

CPC分类号： H05K3/28 ,  B23K1/0016 ,  H05K2203/0574 ,  H05K2203/0588

摘要： According to one example there is a printed circuit board having a first surface and a solder mask over said first surface. There is a layer of sealing material having a shape and location covering a zone of the solder mask which is vulnerable to degradation.

摘要翻译： 根据一个示例，印刷电路板在所述第一表面上具有第一表面和焊料掩模。 存在一层密封材料，其具有覆盖阻焊层的区域的形状和位置，其易于劣化。