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    SEMICONDUCTOR PACKAGE WITH SUBSTRATE PAD
    1.
    发明申请
    SEMICONDUCTOR PACKAGE WITH SUBSTRATE PAD 有权

    公开(公告)号：US20250167087A1

    公开(公告)日：2025-05-22

    申请号：US18775998

    申请日：2024-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dowan Kim ,  Seung Hun Chae ,  Un-Byoung Kang

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

    Abstract: A semiconductor package includes a wiring substrate that includes a wiring pattern, a dielectric pattern that covers the wiring pattern, a substrate pad on the dielectric pattern and including a recess that extends from a top surface of the substrate pad toward an inside of the substrate pad, a metal layer on a bottom surface of the recess and spaced apart from an inner lateral surface of the recess, and a protection layer on the dielectric pattern and covering the substrate pad. The substrate pad penetrates the dielectric pattern to come into connection with the wiring pattern. The protection layer exposes at least a portion of the metal layer. The protection layer extends from the top surface of the substrate pad to fill a space between a lateral surface of the metal layer and the inner lateral surface of the recess.

    Stacked semiconductor package
    4.
    发明授权
    Stacked semiconductor package 有权

    公开(公告)号：US11508685B2

    公开(公告)日：2022-11-22

    申请号：US16992895

    申请日：2020-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

    Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads
    5.
    发明授权
    Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads 有权

    公开(公告)号：US11282792B2

    公开(公告)日：2022-03-22

    申请号：US16805890

    申请日：2020-03-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

    IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

    Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

    Semiconductor package
    8.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12218039B2

    公开(公告)日：2025-02-04

    申请号：US18311621

    申请日：2023-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

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