公开(公告)号：US11282792B2

公开(公告)日：2022-03-22

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20250079362A1

公开(公告)日：2025-03-06

申请号：US18615484

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Kun Jee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: The present disclosure relates to semiconductor packages. An example semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad disposed on a second surface of the second semiconductor chip facing the first surface. The second bonding pad is in contact with the first bonding pad, and includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface. The second semiconductor chip includes a first wiring pad in contact with the fourth surface and a second wiring pad spaced apart from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

公开(公告)号：US20230207532A1

公开(公告)日：2023-06-29

申请号：US18176058

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho JUN ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/1451 ,  H01L2224/06515 ,  H01L2224/0401 ,  H01L2225/06513

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US10818603B2

公开(公告)日：2020-10-27

申请号：US16201380

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Ii Hwan Kim ,  Un Byoung Kang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US10685921B2

公开(公告)日：2020-06-16

申请号：US16198978

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Kun Jee ,  Ji Hwang Kim ,  Un Byoung Kang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

Abstract: A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.

公开(公告)号：US11488910B2

公开(公告)日：2022-11-01

申请号：US17036702

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Il Hwan Kim ,  Un Byoung Kang

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US11222873B2

公开(公告)日：2022-01-11

申请号：US16936882

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US09721930B2

公开(公告)日：2017-08-01

申请号：US15168236

申请日：2016-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoo Lee ,  Minsoo Kim ,  Teak Hoon Lee ,  Young Kun Jee

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

公开(公告)号：US09589947B2

公开(公告)日：2017-03-07

申请号：US14566685

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihwan Hwang ,  Young Kun Jee ,  Jung-Hwan Kim ,  Tae Hong Min ,  Kwang-chul Choi

IPC: H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract translation: 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。

公开(公告)号：US20240194639A1

公开(公告)日：2024-06-13

申请号：US18220053

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon PARK ,  Chungsun Lee ,  Soohwan Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/80379

Abstract: Provided is a semiconductor chip stack structure including a plurality of first semiconductor chip dies stacked in a vertical direction, and one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies, wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.