公开(公告)号：US11488910B2

公开(公告)日：2022-11-01

申请号：US17036702

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Il Hwan Kim ,  Un Byoung Kang

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US10818603B2

公开(公告)日：2020-10-27

申请号：US16201380

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Ii Hwan Kim ,  Un Byoung Kang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US10685921B2

公开(公告)日：2020-06-16

申请号：US16198978

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Kun Jee ,  Ji Hwang Kim ,  Un Byoung Kang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

Abstract: A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.

公开(公告)号：US12074141B2

公开(公告)日：2024-08-27

申请号：US17531115

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Shin ,  Un Byoung Kang ,  Yeong Kwon Ko ,  Jong Ho Lee ,  Teak Hoon Lee ,  Jun Yeong Heo

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

公开(公告)号：US11315802B2

公开(公告)日：2022-04-26

申请号：US16293697

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il Hwan Kim ,  Un Byoung Kang ,  Chung Sun Lee

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

公开(公告)号：US11069541B2

公开(公告)日：2021-07-20

申请号：US16549818

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong Kwon Ko ,  Jun Yeong Heo ,  Un Byoung Kang

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A method for manufacturing a semiconductor device package includes: accommodating a substrate in a cavity in a center of a carrier substrate having the cavity in which a substrate with a semiconductor chip mounted thereon is accommodated in the center, having a support portion in contact with a side wall of the cavity to form an upper surface of the side wall and surrounding the cavity, and formed of a light-transmitting material; defining a molding portion of the substrate by pressing the support portion and an edge region of the substrate; and molding the molding portion, to cover the semiconductor chip.

公开(公告)号：US10930613B2

公开(公告)日：2021-02-23

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick Park ,  Un Byoung Kang ,  Tae Hong Min ,  Teak Hoon Lee ,  Ji Hwan Hwang

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.