公开(公告)号：US11069541B2

公开(公告)日：2021-07-20

申请号：US16549818

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong Kwon Ko ,  Jun Yeong Heo ,  Un Byoung Kang

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A method for manufacturing a semiconductor device package includes: accommodating a substrate in a cavity in a center of a carrier substrate having the cavity in which a substrate with a semiconductor chip mounted thereon is accommodated in the center, having a support portion in contact with a side wall of the cavity to form an upper surface of the side wall and surrounding the cavity, and formed of a light-transmitting material; defining a molding portion of the substrate by pressing the support portion and an edge region of the substrate; and molding the molding portion, to cover the semiconductor chip.

公开(公告)号：US20250046659A1

公开(公告)日：2025-02-06

申请号：US18671011

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Ra Lee ,  Jun Yeong Heo ,  Yeong Kwon Ko

IPC: H01L21/66 ,  H01L21/78 ,  H01L23/00

Abstract: A semiconductor package, which may include a semiconductor chip including a first surface and a second surface, which may be opposite to each other in a first direction. The semiconductor package may include a plurality of first bumps in a first area on the first surface and arranged along a second direction that intersects with the first direction, a plurality of second bumps in a second area on the first surface and arranged along the second direction and spaced apart from the plurality of first bumps in a third direction that intersects with the first direction and the second direction, a first test pad in a third area between the first area and the second area, and a third bump on the first test pad. The first test pad may be along an edge of the semiconductor chip in the third direction.

公开(公告)号：US12074141B2

公开(公告)日：2024-08-27

申请号：US17531115

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Shin ,  Un Byoung Kang ,  Yeong Kwon Ko ,  Jong Ho Lee ,  Teak Hoon Lee ,  Jun Yeong Heo

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

公开(公告)号：US10403603B2

公开(公告)日：2019-09-03

申请号：US15657759

申请日：2017-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Won Park ,  Yeong Kwon Ko

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/46 ,  H01L29/06 ,  H01L23/473 ,  H01L25/065

Abstract: A semiconductor package includes a semiconductor chip in which a side step or a side slope formed toward an inactive surface from an active surface is included and a width of the active surface is smaller than a width of the inactive surface, and an underfill which is disposed on the active surface and positioned at an inner side of the edge of the semiconductor chip.