公开(公告)号：US12125911B2

公开(公告)日：2024-10-22

申请号：US17818595

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3065 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US12125876B2

公开(公告)日：2024-10-22

申请号：US15355783

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Cheng Wang ,  Han-Ti Hsiaw

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823878

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

公开(公告)号：US12119221B2

公开(公告)日：2024-10-15

申请号：US18125509

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Hanhong Chen ,  Philip A. Kraus ,  Joseph AuBuchon

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/34 ,  C23C16/45542 ,  H01L21/0217 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02274

Abstract: A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.

公开(公告)号：US12107005B2

公开(公告)日：2024-10-01

申请号：US17491684

申请日：2021-10-01

Applicant: ASM IP Holding B.V.

Inventor： Zecheng Liu ,  Viljami Pore ,  Tommi Paavo Tynell ,  Yu Xu ,  Mikko Ruoho

IPC: H01L21/768 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01J37/32146 ,  H01J37/32449 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01J2237/332

Abstract: The current disclosure relates to methods of depositing silicon-containing material on a substrate comprising a gap, wherein the method comprises providing the substrate in a reaction chamber and depositing a carbon-containing inhibition layer on the substrate, and depositing silicon-containing material on the substrate. Depositing the inhibition layer comprises supplying a carbon precursor comprising carbon in the reaction chamber and supplying first plasma in the reaction chamber to form a first reactive species from the carbon precursor for forming the inhibition layer on the substrate. The inhibition layer is deposited preferentially in the vicinity of the top of the gap. The disclosure further relates to methods of forming a structure, methods of manufacturing a device and to a semiconductor processing apparatus.

公开(公告)号：US20240321787A1

公开(公告)日：2024-09-26

申请号：US18678306

申请日：2024-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lung SHIH ,  Chao-Keng LI ,  Alan KUO ,  C. C. CHANG ,  Yi-An LIN

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L24/03 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76837 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/0391 ,  H01L2224/1191 ,  H01L2924/30205

Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.

公开(公告)号：US20240321572A1

公开(公告)日：2024-09-26

申请号：US18186778

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Fong Lin ,  Yen-Chun Huang ,  Zhen-Cheng Wu ,  Chi On Chui ,  Chih-Tang Peng ,  Yu Ying Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L21/0228 ,  H01L21/0217 ,  H01L21/28123 ,  H01L21/76224

Abstract: Provided are semiconductor devices and methods for manufacturing semiconductor devices. A method deposits conformal material to form a conformal liner in the trench and modifies the conformal liner such an upper liner portion is modified more than a lower liner portion. The deposition and modifying steps are repeated while a rate of deposition of the conformal material over a non-modified surface of the conformal liner is faster than a rate of deposition of the conformal material over a modified surface of the conformal liner to form a remaining unfilled gap with a V-shape. The method further includes depositing a conformal material in the remaining unfilled gap.

公开(公告)号：US20240309507A1

公开(公告)日：2024-09-19

申请号：US18612809

申请日：2024-03-21

Applicant: Lam Research Corporation

Inventor： Fayaz Shaikh ,  Nick Linebarger ,  Curtis Bailey

IPC: C23C16/455 ,  C23C16/04 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

CPC classification number: C23C16/45574 ,  C23C16/04 ,  C23C16/45519 ,  C23C16/45565 ,  C23C16/45597 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/67017 ,  H01L21/68735 ,  H01L21/68771 ,  H01L21/68785 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/67161

Abstract: A plasma processing system is provided. The system includes a chamber, a controller and a showerhead disposed in the chamber. A first gas manifold is connected to the showerhead for providing a first gas from a first gas source responsive to control from the controller. A shower-pedestal is disposed in the chamber and oriented opposite the showerhead. A second gas manifold is connected to the shower-pedestal for providing a second gas from a second gas source responsive to control from the controller. A substrate support for holding a substrate at a spaced apart relationship from the shower-pedestal is provided. A radio frequency (RF) power supply for providing power to the showerhead to generate a plasma is provided. The plasma is used for depositing a film on a back-side of the substrate, when present in the chamber. The substrate is held by the substrate support in the spaced apart relationship from the shower-pedestal, during backside deposition. The showerhead provides a purge gas during the backside deposition.

公开(公告)号：US20240297039A1

公开(公告)日：2024-09-05

申请号：US18640095

申请日：2024-04-19

Applicant: ASM IP Holding B.V.

Inventor： Charles Dezelah ,  Hideaki Fukuda ,  Viljami J. Pore

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/455 ,  C23C16/52 ,  H01J37/32

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/45553 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32449 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/0228 ,  H01J2237/332

Abstract: The current disclosure relates to a vapor deposition assembly for depositing silicon nitride on a substrate by a plasma-enhanced cyclic deposition process. The disclosure also relates to a method for depositing silicon nitride on a substrate by a plasma-enhanced cyclic deposition process. The method comprises providing a substrate in a reaction chamber, providing a vapor-phase silicon precursor according to the formula SiH3X, wherein X is iodine or bromine, into the reaction chamber, removing excess silicon precursor and possible reaction byproducts from the reaction chamber and providing a reactive species generated from a nitrogen-containing plasma into the reaction chamber to form silicon nitride on the substrate. The disclosure further relates to structure and devices formed by the method.

公开(公告)号：US20240258104A1

公开(公告)日：2024-08-01

申请号：US18560924

申请日：2022-05-04

Applicant: JUSUNG ENGINEERING CO., LTD.

Inventor： Yoon Jeong KIM ,  Jung Kyun LEE

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02315 ,  H01L21/0234 ,  H01L29/1608 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2029/42388

Abstract: The present disclosure relates to a method for depositing a thin film, and more particularly, to a method for depositing a thin film, which forms a gate insulation film on a silicon carbide substrate.
In accordance with an exemplary embodiment, a method for depositing a thin film includes: preparing a silicon carbide substrate having a plurality of semiconductor regions; and forming a gate insulation film on the silicon carbide substrate at a temperature of 100° C. to 400° C. through an atomic layer deposition process.

公开(公告)号：US20240249934A1

公开(公告)日：2024-07-25

申请号：US18626864

申请日：2024-04-04

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  Bhaskar Jyoti Bhuyan ,  Hsueh Chung Chen ,  Scott A. DeVries ,  Raghuveer Satya Makala

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/768

CPC classification number: H01L21/0217 ,  C23C16/45544 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02326 ,  H01L21/76831 ,  H01L21/02046 ,  H01L21/02052

Abstract: Methods of manufacturing electronic devices, e.g., logic devices or memory devices, are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; pre-treating the top surface of the film stack to form a treated surface; exposing the treated surface to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.