公开(公告)号：US20240361915A1

公开(公告)日：2024-10-31

申请号：US18765095

申请日：2024-07-05

Applicant: KIOXIA CORPORATION

Inventor： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/88 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

公开(公告)号：US12032831B2

公开(公告)日：2024-07-09

申请号：US17880546

申请日：2022-08-03

Applicant: KIOXIA CORPORATION

Inventor： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/88 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

公开(公告)号：US11984181B2

公开(公告)日：2024-05-14

申请号：US16457166

申请日：2019-06-28

Applicant: Western Digital Technologies, Inc.

Inventor： Srinivasan Seetharaman ,  Sourabh Sankule ,  Piyush Girish Sagdeo

IPC: G11C29/44 ,  G06F11/20 ,  G11C29/38 ,  G11C29/04

CPC classification number: G11C29/44 ,  G06F11/2094 ,  G11C29/38 ,  G06F2201/82 ,  G11C2029/0409

Abstract: The disclosure relates in some aspects to a design for a data storage apparatus with a non-volatile memory that includes a block of memory comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a failure in a first sub-block. The second sub-block is then marked, in response to a failure detection in the first sub-block, with an initial designation as an unusable sub-block, and a test of the second sub-block is performed to determine a usability of the second sub-block. Based on the test, the second sub-block is then marked with a second designation that is one of a tested usable sub-block or a tested unusable sub-block.

公开(公告)号：US11903210B2

公开(公告)日：2024-02-13

申请号：US17376856

申请日：2021-07-15

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: H10B43/30 ,  H01L25/065 ,  H10B43/20 ,  H10B43/27 ,  H10B43/50 ,  G11C5/04 ,  H01L23/00 ,  H01L29/792 ,  H01L21/822 ,  H01L21/28 ,  G11C29/02 ,  H10B43/40 ,  G11C29/04

CPC classification number: H10B43/30 ,  G11C5/04 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H01L21/8221 ,  H01L24/16 ,  H01L25/0657 ,  H01L29/40117 ,  H01L29/792 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  G11C2029/0409 ,  H01L2224/16145 ,  H01L2225/06517

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

公开(公告)号：US11768732B2

公开(公告)日：2023-09-26

申请号：US17530748

申请日：2021-11-19

Applicant: KIOXIA CORPORATION

Inventor： Yuta Kumano ,  Hironori Uchikawa ,  Kosuke Morinaga ,  Naoaki Kokubun ,  Masahiro Kiyooka ,  Yoshiki Notani ,  Kenji Sakurada ,  Daiki Watanabe

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  H03M13/00 ,  H03M13/37 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  G11C16/26 ,  G11C29/42

CPC classification number: G06F11/1048 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/52 ,  H03M13/3715 ,  H03M13/3746 ,  H03M13/6325 ,  G11C16/26 ,  G11C29/42 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

公开(公告)号：US11710534B1

公开(公告)日：2023-07-25

申请号：US17682837

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Christian N. Mohr ,  Scott E. Smith ,  Manoj Vijay

IPC: G11C29/52 ,  G11C29/02 ,  G11C29/46 ,  G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/04

CPC classification number: G11C29/52 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/38 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0409

Abstract: Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.

公开(公告)号：US20190253050A1

公开(公告)日：2019-08-15

申请号：US16397630

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett

IPC: H03K17/284 ,  G11C7/12 ,  G11C5/14 ,  G11C7/22 ,  H03K19/00 ,  G11C8/10 ,  G11C29/02 ,  G11C7/06 ,  G11C7/04 ,  H03K19/003

CPC classification number: H03K17/284 ,  G11C5/148 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/5006 ,  H03K19/0016 ,  H03K19/00384 ,  H03K2217/0036

Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

公开(公告)号：US20190220346A1

公开(公告)日：2019-07-18

申请号：US15871594

申请日：2018-01-15

Applicant: Microchip Technology Incorporated

Inventor： Alain Vergnes ,  Eric Matulik ,  Marc Maunier

IPC: G06F11/07 ,  G06F13/16 ,  G06F3/06 ,  G06F11/08

CPC classification number: G06F11/0796 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0629 ,  G06F11/08 ,  G06F13/1689 ,  G11C29/022 ,  G11C29/08 ,  G11C29/10 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/3602

Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

公开(公告)号：US20190146671A1

公开(公告)日：2019-05-16

申请号：US16243956

申请日：2019-01-09

Applicant: International Business Machines Corporation

Inventor： Charles J. Camp ,  Timothy J. Fisher ,  Aaron D. Fry ,  Nikolas Ioannou ,  Ioannis Koltsidas ,  Nikolaos Papandreou ,  Thomas Parnell ,  Roman A. Pletka ,  Charalampos Pozidis ,  Sasa Tomic

IPC: G06F3/06 ,  G11C29/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVSΔ) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVSΔ values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVSΔ values, or both the TVSBASE value and the one or more TVSΔ values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.

公开(公告)号：US20190102289A1

公开(公告)日：2019-04-04

申请号：US16190017

申请日：2018-11-13

Applicant: Wolley Inc.

Inventor： Chuen-Shen Bernard Shung

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/0804 ,  G06F12/1009 ,  G11C29/04

CPC classification number: G06F12/0238 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0685 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/403 ,  G06F2212/608 ,  G06F2212/7211 ,  G11C29/52 ,  G11C2029/0409

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.