公开(公告)号：US11768732B2

公开(公告)日：2023-09-26

申请号：US17530748

申请日：2021-11-19

Applicant: KIOXIA CORPORATION

Inventor： Yuta Kumano ,  Hironori Uchikawa ,  Kosuke Morinaga ,  Naoaki Kokubun ,  Masahiro Kiyooka ,  Yoshiki Notani ,  Kenji Sakurada ,  Daiki Watanabe

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  H03M13/00 ,  H03M13/37 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  G11C16/26 ,  G11C29/42

CPC classification number: G06F11/1048 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/52 ,  H03M13/3715 ,  H03M13/3746 ,  H03M13/6325 ,  G11C16/26 ,  G11C29/42 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

公开(公告)号：US11909415B2

公开(公告)日：2024-02-20

申请号：US17694057

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Masahiro Kiyooka ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: H03M13/11 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/09

CPC classification number: H03M13/1125 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/098 ,  H03M13/1108

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.