公开(公告)号：US11664063B2

公开(公告)日：2023-05-30

申请号：US17444925

申请日：2021-08-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Simon J. Lovett

IPC: G11C7/00 ,  G11C11/406 ,  G06F7/58 ,  H03K3/84

CPC classification number: G11C11/40611 ,  G06F7/584 ,  G11C11/40615 ,  H03K3/84

Abstract: Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

公开(公告)号：US11581889B2

公开(公告)日：2023-02-14

申请号：US16397630

申请日：2019-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Simon J. Lovett

IPC: H03K17/284 ,  G11C7/04 ,  H03K19/00 ,  H03K19/003 ,  G11C5/14 ,  G11C29/02 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C8/06 ,  G11C29/04 ,  G11C29/50

Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

公开(公告)号：US11521670B2

公开(公告)日：2022-12-06

申请号：US17096476

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett

IPC: G11C8/08 ,  G11C11/408 ,  G11C7/02 ,  G11C8/14

Abstract: Memory devices including word lines coupled to pull-down transistors are disclosed. A memory device may include a number of memory cells, a first word line, and a second word line. The first word line may be configured to apply a voltage to a number of transistors to access at least one of the number of memory cells. The first word line may include a first portion electrically coupled to a first driver and a second portion electrically coupled to a gate of a pull-down transistor. The second word line may be positioned adjacent to the first word line. The second word line may include a third portion electrically coupled to a second driver and a fourth portion electrically coupled to a terminal of the pull-down transistor. Associated systems are also disclosed.

公开(公告)号：US11087835B2

公开(公告)日：2021-08-10

申请号：US16927682

申请日：2020-07-13

Applicant: Micron Technology, inc.

Inventor： Hiroshi Akamatsu ,  Simon J. Lovett

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412

Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.

公开(公告)号：US09508409B2

公开(公告)日：2016-11-29

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US20220148642A1

公开(公告)日：2022-05-12

申请号：US17096476

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett

IPC: G11C11/408

Abstract: Memory devices including word lines coupled to pull-down transistors are disclosed. A memory device may include a number of memory cells, a first word line, and a second word line. The first word line may be configured to apply a voltage to a number of transistors to access at least one of the number of memory cells. The first word line may include a first portion electrically coupled to a first driver and a second portion electrically coupled to a gate of a pull-down transistor. The second word line may be positioned adjacent to the first word line. The second word line may include a third portion electrically coupled to a second driver and a fourth portion electrically coupled to a terminal of the pull-down transistor. Associated systems are also disclosed.

公开(公告)号：US11295832B2

公开(公告)日：2022-04-05

申请号：US16950613

申请日：2020-11-17

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett ,  Richard E. Fackenthal

IPC: G11C29/00 ,  G11C29/50 ,  G11C11/22

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.

公开(公告)号：US10734067B1

公开(公告)日：2020-08-04

申请号：US16551432

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Simon J. Lovett

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412

Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.

公开(公告)号：US20200075063A1

公开(公告)日：2020-03-05

申请号：US16118837

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett

IPC: G11C5/14 ,  H03K19/20 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/20

Abstract: A semiconductor device may include a local power domain configured to selectively provide or prevent power to a logic block of the memory device and a temperature sensor located on the semiconductor device. The semiconductor device may also include timeout circuitry to delay a power down of the local power domain by a timeout time based at least in part on temperature information from the temperature sensor.

公开(公告)号：US20200013478A1

公开(公告)日：2020-01-09

申请号：US16513018

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett ,  Richard E. Fackenthal

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.