公开(公告)号：US20240113202A1

公开(公告)日：2024-04-04

申请号：US18526084

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823814

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US11855182B2

公开(公告)日：2023-12-26

申请号：US17090121

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823814

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US20210020772A1

公开(公告)日：2021-01-21

申请号：US17063206

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ken Lin ,  Chun Te Li ,  Chih-Peng Hsu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

公开(公告)号：US20210202235A1

公开(公告)日：2021-07-01

申请号：US17201691

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US11450772B2

公开(公告)日：2022-09-20

申请号：US17063206

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ken Lin ,  Chun Te Li ,  Chih-Peng Hsu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

公开(公告)号：US20210210354A1

公开(公告)日：2021-07-08

申请号：US17206740

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin Wang ,  Hung-Ju Chou ,  Jiun-Ming Kuo ,  Wei-Ken Lin ,  Chun Te Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further incudes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

公开(公告)号：US20190148514A1

公开(公告)日：2019-05-16

申请号：US15812966

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US09824943B2

公开(公告)日：2017-11-21

申请号：US15082399

申请日：2016-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Wei-Ken Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L21/762 ,  H01L21/66 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L22/26 ,  H01L21/31105 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L29/7846 ,  H01L29/785

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

公开(公告)号：US20230326746A1

公开(公告)日：2023-10-12

申请号：US18326370

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L29/36 ,  H01L21/266 ,  H01L21/762

CPC classification number: H01L21/0228 ,  H01L27/0886 ,  H01L21/02211 ,  H01L21/823468 ,  H01L21/02208 ,  H01L21/02205 ,  H01L21/31111 ,  H01L21/02126 ,  H01L21/0214 ,  H01L29/6656 ,  H01L21/823431 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/3065 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/823481 ,  H01L21/31053 ,  H01L29/36 ,  H01L21/266 ,  H01L29/66795 ,  H01L21/76224

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such

公开(公告)号：US20220230871A1

公开(公告)日：2022-07-21

申请号：US17712561

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.