公开(公告)号：US20210391209A1

公开(公告)日：2021-12-16

申请号：US17443506

申请日：2021-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US20210082802A1

公开(公告)日：2021-03-18

申请号：US16571805

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen HUANG ,  Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L21/768

Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material.

公开(公告)号：US20190259658A1

公开(公告)日：2019-08-22

申请号：US16399273

申请日：2019-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

公开(公告)号：US20190131408A1

公开(公告)日：2019-05-02

申请号：US16227592

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ching-Fu YEH ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20180033727A1

公开(公告)日：2018-02-01

申请号：US15220078

申请日：2016-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US20170210613A1

公开(公告)日：2017-07-27

申请号：US15007852

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B81B3/00

CPC classification number: B81B3/0021 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/09 ,  B81C1/00246 ,  B81C2203/0136 ,  B81C2203/0771

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer. The beam structure includes a fixed portion and a moveable portion, the fixed portion is extended vertically, and the movable portion is extended horizontally. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.

公开(公告)号：US20180350913A1

公开(公告)日：2018-12-06

申请号：US15675535

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ching-Fu YEH ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L29/1606 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20180308947A1

公开(公告)日：2018-10-25

申请号：US15615901

申请日：2017-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Yung-Chih WANG ,  Shin-Yi YANG ,  Chih-Wei LU ,  Hsin-Ping CHEN ,  Shau-Lin SHUE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/49 ,  H01L21/76885 ,  H01L29/0649 ,  H01L29/12 ,  H01L29/435 ,  H01L29/66666

Abstract: A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.

公开(公告)号：US20180164698A1

公开(公告)日：2018-06-14

申请号：US15586881

申请日：2017-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsiang-Wei LIU ,  Shau-Lin SHUE ,  Li-Lin SU ,  Yung-Hsu WU

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20170287842A1

公开(公告)日：2017-10-05

申请号：US15632184

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.