公开(公告)号：US20180164698A1

公开(公告)日：2018-06-14

申请号：US15586881

申请日：2017-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsiang-Wei LIU ,  Shau-Lin SHUE ,  Li-Lin SU ,  Yung-Hsu WU

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20240321573A1

公开(公告)日：2024-09-26

申请号：US18678463

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Yung-Hsu WU ,  Cheng-Chin LEE ,  Hai-Ching CHEN ,  Hsin-Yen HUANG ,  Shau-Lin SHUE

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20200343180A1

公开(公告)日：2020-10-29

申请号：US16926942

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.

公开(公告)号：US20190067187A1

公开(公告)日：2019-02-28

申请号：US15689784

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.