公开(公告)号：US20210391209A1

公开(公告)日：2021-12-16

申请号：US17443506

申请日：2021-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US20210082802A1

公开(公告)日：2021-03-18

申请号：US16571805

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen HUANG ,  Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L21/768

Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material.

公开(公告)号：US20170194242A1

公开(公告)日：2017-07-06

申请号：US15063358

申请日：2016-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen HUANG ,  Kai-Fang CHENG ,  Chi-Lin TENG ,  Shao-Kuan LEE ,  Hai-Ching CHEN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76865 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

公开(公告)号：US20220310442A1

公开(公告)日：2022-09-29

申请号：US17806726

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L21/02

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

公开(公告)号：US20210134666A1

公开(公告)日：2021-05-06

申请号：US17121661

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yen HUANG ,  Kai-Fang CHENG ,  Chi-Lin TENG ,  Shao-Kuan LEE ,  Hai-Ching CHEN

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

公开(公告)号：US20210249299A1

公开(公告)日：2021-08-12

申请号：US16788057

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

公开(公告)号：US20170263549A1

公开(公告)日：2017-09-14

申请号：US15067807

申请日：2016-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76835 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.

公开(公告)号：US20240321573A1

公开(公告)日：2024-09-26

申请号：US18678463

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Yung-Hsu WU ,  Cheng-Chin LEE ,  Hai-Ching CHEN ,  Hsin-Yen HUANG ,  Shau-Lin SHUE

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20200020580A1

公开(公告)日：2020-01-16

申请号：US16035455

申请日：2018-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

Abstract: A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.

公开(公告)号：US20200006116A1

公开(公告)日：2020-01-02

申请号：US16270057

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan LEE ,  Cheng-Chin Lee ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.