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    Metal Capping Layer and Methods Thereof
    1.
    发明申请
    Metal Capping Layer and Methods Thereof 有权

    公开(公告)号：US20210391209A1

    公开(公告)日：2021-12-16

    申请号：US17443506

    申请日：2021-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan LEE ,  Cheng-Chin LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

    Selective Deposition of Barrier Layer
    4.
    发明公开
    Selective Deposition of Barrier Layer 审中-公开

    公开(公告)号：US20240266211A1

    公开(公告)日：2024-08-08

    申请号：US18618044

    申请日：2024-03-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

    CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0228 ,  H01L21/30604 ,  H01L21/31116

    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

    INTERCONNECT STRUCTURES INCLUDING AIR GAPS
    5.
    发明申请
    INTERCONNECT STRUCTURES INCLUDING AIR GAPS 有权

    公开(公告)号：US20220310442A1

    公开(公告)日：2022-09-29

    申请号：US17806726

    申请日：2022-06-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L21/02

    Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20200020580A1

    公开(公告)日：2020-01-16

    申请号：US16035455

    申请日：2018-07-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

    Abstract: A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.

    METAL CAPPING LAYER AND METHODS THEREOF
    10.
    发明申请
    METAL CAPPING LAYER AND METHODS THEREOF 审中-公开

    公开(公告)号：US20200006116A1

    公开(公告)日：2020-01-02

    申请号：US16270057

    申请日：2019-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan LEE ,  Cheng-Chin Lee ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

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