公开(公告)号：US20170210613A1

公开(公告)日：2017-07-27

申请号：US15007852

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B81B3/00

CPC classification number: B81B3/0021 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/09 ,  B81C1/00246 ,  B81C2203/0136 ,  B81C2203/0771

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer. The beam structure includes a fixed portion and a moveable portion, the fixed portion is extended vertically, and the movable portion is extended horizontally. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.

公开(公告)号：US20210035853A1

公开(公告)日：2021-02-04

申请号：US17065253

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsin-Ping CHEN ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.

公开(公告)号：US20190326157A1

公开(公告)日：2019-10-24

申请号：US16458399

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsin-Ping CHEN ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

公开(公告)号：US20190097010A1

公开(公告)日：2019-03-28

申请号：US15719301

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chih WANG ,  Yu-Chieh LIAO ,  Tai-I YANG ,  Hsin-Ping CHEN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.

公开(公告)号：US20220238676A1

公开(公告)日：2022-07-28

申请号：US17718080

申请日：2022-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chih WANG ,  Yu-Chieh LIAO ,  Tai-I YANG ,  Hsin-Ping CHEN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786

Abstract: A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.

公开(公告)号：US20190305100A1

公开(公告)日：2019-10-03

申请号：US16443769

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chih WANG ,  Yu-Chieh LIAO ,  Tai-I YANG ,  Hsin-Ping CHEN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.

公开(公告)号：US20190067089A1

公开(公告)日：2019-02-28

申请号：US15691035

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Li-Lin SU ,  Shin-Yi YANG ,  Cheng-Chi CHUANG ,  Hsin-Ping CHEN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

公开(公告)号：US20180308947A1

公开(公告)日：2018-10-25

申请号：US15615901

申请日：2017-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Yung-Chih WANG ,  Shin-Yi YANG ,  Chih-Wei LU ,  Hsin-Ping CHEN ,  Shau-Lin SHUE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/49 ,  H01L21/76885 ,  H01L29/0649 ,  H01L29/12 ,  H01L29/435 ,  H01L29/66666

Abstract: A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.

公开(公告)号：US20200299129A1

公开(公告)日：2020-09-24

申请号：US16895446

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B82B1/00 ,  B81C1/00 ,  B81B3/00 ,  B82B3/00

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a first dielectric layer formed over a substrate, and a first conductive layer formed in the first dielectric layer. The NEMS device structure includes a second dielectric layer formed over the first dielectric layer, and a first supporting electrode a second supporting electrode and a beam structure formed in the second dielectric layer. The beam structure is formed between the first supporting electrode and the second supporting electrode, and the beam structure has a T-shaped structure. The NEMS device structure includes a first through hole formed between the first supporting electrode and the beam structure, and a second through hole formed between the second supporting electrode and the beam structure.

公开(公告)号：US20190245054A1

公开(公告)日：2019-08-08

申请号：US16390210

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Yung-Chih WANG ,  Shin-Yi YANG ,  Chih-Wei LU ,  Hsin-Ping CHEN ,  Shau-Lin SHUE

IPC: H01L29/49 ,  H01L29/43 ,  H01L29/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L29/49 ,  H01L21/76885 ,  H01L29/0649 ,  H01L29/12 ,  H01L29/435 ,  H01L29/66666 ,  H01L29/78642

Abstract: A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.