-
公开(公告)号：US20240136226A1
公开(公告)日：2024-04-25
申请号：US18401989
申请日：2024-01-02
发明人： Li-Wei CHU , Ying-Chi SU , Yu-Kai CHEN , Wei-Yip LOH , Hung-Hsu CHEN , Chih-Wei CHANG , Ming-Hsing TSAI
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205
CPC分类号： H01L21/76897 , H01L21/02068 , H01L21/02123 , H01L21/32053
摘要： An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
-
2.发明公开公开(公告)号：US20230299168A1
公开(公告)日：2023-09-21
申请号：US17695075
申请日：2022-03-15
发明人： Kuan-Kan HU , Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Hsu-Kai CHANG , Ken-Yu CHANG , Wei-Yip LOH , Hung-Yi HUANG , Harry CHIEN , Sung-Li WANG , Pinyen LIN , Chuan-Hui SHEN , Tzu-Pei CHEN , Yuting CHENG
IPC分类号： H01L29/45 , H01L29/40 , H01L29/417
CPC分类号： H01L29/45 , H01L29/401 , H01L29/41791 , H01L29/41733 , H01L23/5226
摘要： A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.
-
公开(公告)号：US20230260847A1
公开(公告)日：2023-08-17
申请号：US18308952
申请日：2023-04-28
发明人： Wei-Yip LOH , Yan-Ming TSAI , Yi-Ning TAI , Raghunath PUTIKAM , Hung-Yi HUANG , Hung-Hsu CHEN , Chih-Wei CHANG
IPC分类号： H01L21/8238 , H01L29/40
CPC分类号： H01L21/823814 , H01L29/401 , H01L21/823821 , H01L21/823871 , H01L29/41791
摘要： Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
-
公开(公告)号：US20230230916A1
公开(公告)日：2023-07-20
申请号：US17577800
申请日：2022-01-18
发明人： Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Tzu-Pei CHEN , Ken-Yu CHANG , Hung-Yi HUANG , Harry CHIEN , Wei-Yip LOH , Chun-I TSAI , Hong-Mao LEE , Sung-Li WANG , Pinyen LIN
IPC分类号： H01L23/522 , H01L29/40 , H01L21/768
CPC分类号： H01L23/5226 , H01L29/401 , H01L21/76877 , H01L21/76843
摘要： A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
-
公开(公告)号：US20230411496A1
公开(公告)日：2023-12-21
申请号：US17750996
申请日：2022-05-23
发明人： Kan-Ju LIN , Chien CHANG , Chih-Shiun CHOU , Tai Min CHANG , Yi-Ning TAI , Hong-Mao LEE , Yan-Ming TSAI , Wei-Yip LOH , Harry CHIEN , Chih-Wei CHANG , Ming-Hsing TSAI , Lin-Yu HUANG
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/7851 , H01L29/41791 , H01L21/823418
摘要： A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.
-
6.发明公开公开(公告)号：US20230402366A1
公开(公告)日：2023-12-14
申请号：US17836781
申请日：2022-06-09
发明人： Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Hsu-Kai CHANG , Kuan-Kan HU , Ken-Yu CHANG , Hung-Yi HUANG , Harry CHIEN , Wei-Yip LOH , Chun-I TSAI , Hong-Mao LEE , Sung-Li WANG , Pinyen LIN , Chuan-Hui SHEN
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/53266 , H01L21/76843 , H01L21/76883
摘要： A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.
-
公开(公告)号：US20230054633A1
公开(公告)日：2023-02-23
申请号：US17445431
申请日：2021-08-19
发明人： Wei-Yip LOH , Yan-Ming TSAI , Yi-Ning TAI , Raghunath PUTIKAM , Hung-Yi HUANG , Hung-Hsu CHEN , Chih-Wei CHANG
IPC分类号： H01L21/8238 , H01L29/40
摘要： Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
-
公开(公告)号：US20220328350A1
公开(公告)日：2022-10-13
申请号：US17809109
申请日：2022-06-27
发明人： Li-Wei CHU , Ying-Chi SU , Yu-Kai CHEN , Wei-Yip LOH , Hung-Hsu CHEN , Chih-Wei CHANG , Ming-Hsing TSAI
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205
摘要： An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.037 秒)
