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1.发明授权公开(公告)号：US12094540B2
公开(公告)日：2024-09-17
申请号：US18103754
申请日：2023-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won-Taeck Jung , Sang-Wan Nam , Jinwoo Park , Jaeyong Jeong
IPC: G11C16/16 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/20 , G11C16/34 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC classification number: G11C16/20 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
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2.发明公开公开(公告)号：US20230273880A1
公开(公告)日：2023-08-31
申请号：US18312109
申请日：2023-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon YOON , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
CPC classification number: G06F12/0646 , G11C5/025 , G11C16/0483 , G11C11/5642 , G11C11/5628 , G11C8/10 , G06F3/0679 , G06F3/0653 , G06F3/0619 , G11C16/08 , G11C16/24 , G06F2212/2022 , G11C2211/5648
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US11515325B2
公开(公告)日：2022-11-29
申请号：US17025479
申请日：2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11556 , H01L27/11526 , G11C8/14 , H01L27/11519
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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公开(公告)号：US10892019B2
公开(公告)日：2021-01-12
申请号：US16788638
申请日：2020-02-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan Nam , Dong-Hun Kwak , Chi-Weon Yoon
IPC: G11C16/04 , G11C16/16 , G11C8/12 , H01L27/11573 , H01L27/11582 , G11C16/14
Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
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5.发明授权公开(公告)号：US10671529B2
公开(公告)日：2020-06-02
申请号：US15790583
申请日：2017-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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Patent Agency Ranking
公开(公告)号：US09627086B2
公开(公告)日：2017-04-18
申请号：US14811380
申请日：2015-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
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公开(公告)号：US09449699B2
公开(公告)日：2016-09-20
申请号：US15009856
申请日：2016-01-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Won-Taeck Jung , Junghoon Park
CPC classification number: G11C16/14 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3418 , G11C16/344 , G11C16/3445 , H01L27/115
Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
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公开(公告)号：US08982642B2
公开(公告)日：2015-03-17
申请号：US14485049
申请日：2014-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan Nam , Won-Teack Jung , Junghoon Park
CPC classification number: G11C16/14 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3418 , G11C16/344 , G11C16/3445 , H01L27/115
Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
Abstract translation: 非易失性存储器的擦除方法包括向衬底提供擦除电压，将选择字线电压提供给与非易失性存储器的存储块内的选定子块相连的字线，将非选择字线电压提供给 在从提供擦除电压的时间点起的第一延迟时间期间，与存储器块内的未选择子块相连的字线，然后浮动与未选择的子块相连的字线。
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公开(公告)号：USRE50325E1
公开(公告)日：2025-03-04
申请号：US17585800
申请日：2022-01-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Kitae Park
Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
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10.发明授权公开(公告)号：US12176046B2
公开(公告)日：2024-12-24
申请号：US17955858
申请日：2022-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yohan Lee , Sang-Wan Nam , Sang-Won Park , Jiho Cho , Eunhyang Park
Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.
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