公开(公告)号：US20230273880A1

公开(公告)日：2023-08-31

申请号：US18312109

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi Weon YOON ,  Dong Hyuk Chae ,  Sang-Wan Nam ,  Jung-Yun Yun

IPC: G06F12/06 ,  G11C5/02 ,  G11C16/04 ,  G11C11/56 ,  G11C8/10 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24

CPC classification number: G06F12/0646 ,  G11C5/025 ,  G11C16/0483 ,  G11C11/5642 ,  G11C11/5628 ,  G11C8/10 ,  G06F3/0679 ,  G06F3/0653 ,  G06F3/0619 ,  G11C16/08 ,  G11C16/24 ,  G06F2212/2022 ,  G11C2211/5648

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

公开(公告)号：US20200294601A1

公开(公告)日：2020-09-17

申请号：US16891455

申请日：2020-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Hun KWAK ,  Sang Wan NAM ,  Chi Weon YOON

IPC: G11C16/10 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

公开(公告)号：US20180277206A1

公开(公告)日：2018-09-27

申请号：US15795245

申请日：2017-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Kook PARK ,  Jung SUNWOO ,  Chi Weon YOON

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2213/71

Abstract: An operating method of a memory device is provided. Using a statistical model, a resistance Rdyn of a variable resistor of a memory cell and a variation ΔRdyn of the resistance Rdyn are determined. Based on the resistance Rdyn and the variation ΔRdyn of the resistance Rdyn, an average resistance Rdyn_avg and a beta value of the variable resistor are determined. Then, using the average resistance Rdyn_avg and the beta value, a resistance Ra of an insertion resistor, connected between the memory cell and a power supply generator for generating a power supply voltage VPGM, is determined.

公开(公告)号：US20180046574A1

公开(公告)日：2018-02-15

申请号：US15790583

申请日：2017-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

IPC: G06F12/06 ,  G11C11/56 ,  G11C8/10 ,  G11C5/02 ,  G06F3/06 ,  G11C16/04

CPC classification number: G06F12/0646 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F2212/2022 ,  G11C5/025 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C2211/5648

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

公开(公告)号：US20200242030A1

公开(公告)日：2020-07-30

申请号：US16849645

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

IPC: G06F12/06 ,  G11C11/56 ,  G06F3/06 ,  G11C16/24 ,  G11C5/02 ,  G11C16/08 ,  G11C16/04 ,  G11C8/10

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

公开(公告)号：US20190259456A1

公开(公告)日：2019-08-22

申请号：US16125905

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hun KWAK ,  Sang Wan NAM ,  Chi Weon YOON

IPC: G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.

公开(公告)号：US20190214088A1

公开(公告)日：2019-07-11

申请号：US16111539

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hun KWAK ,  Sang Wan NAM ,  Chi Weon YOON

IPC: G11C16/10 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

公开(公告)号：US20210193679A1

公开(公告)日：2021-06-24

申请号：US16993570

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Chan Ho KIM ,  Kyung Hwa YUN ,  Dae Seok BYEON ,  Chi Weon YOON

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

公开(公告)号：US20210117321A1

公开(公告)日：2021-04-22

申请号：US17137942

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

IPC: G06F12/06 ,  G11C5/02 ,  G11C16/04 ,  G11C11/56 ,  G11C8/10 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

公开(公告)号：US20190214067A1

公开(公告)日：2019-07-11

申请号：US16043474

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Wan NAM ,  Dong Hun KWAK ,  Wan Dong KIM ,  Chi Weon YOON

IPC: G11C8/14 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.