公开(公告)号：US12289908B2

公开(公告)日：2025-04-29

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin Jeong ,  Do Hyun Go ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Min-Hee Choi ,  Ryong Ha

IPC: H10D30/67 ,  H10D62/13

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20180114727A1

公开(公告)日：2018-04-26

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US20230253449A1

公开(公告)日：2023-08-10

申请号：US17935528

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk Shin ,  Hyun-Kwan Yu ,  Seok Hoon Kim ,  Pan Kwi Park ,  Yong Seung Kim ,  Jung Taek Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4232 ,  H01L29/66553

Abstract: A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

公开(公告)号：US10790133B2

公开(公告)日：2020-09-29

申请号：US15416408

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Sun Jung Kim ,  Yi Hwan Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Hyun Kwan Yu ,  Seung Hun Lee

IPC: B08B7/00 ,  B08B7/04 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687 ,  H01L29/66 ,  H01J37/32 ,  H01L21/683 ,  H01L29/78 ,  H01L29/165

Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.

公开(公告)号：US11942551B2

公开(公告)日：2024-03-26

申请号：US17519967

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US11821106B2

公开(公告)日：2023-11-21

申请号：US15869905

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Gyeom Kim ,  Yi Hwan Kim ,  Sun Jung Kim ,  Pan Kwi Park ,  Jeong Ho Yoo

IPC: C30B25/12 ,  C23C16/458 ,  H01L29/66 ,  H01L29/08

CPC classification number: C30B25/12 ,  C23C16/4585 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.

公开(公告)号：US20230145260A1

公开(公告)日：2023-05-11

申请号：US17831513

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including: a plurality of fin-shaped patterns spaced apart from each other in a first direction and extending in a second direction on a substrate; a field insulating layer covering sidewalls of the plurality of fin-shaped patterns and disposed between the fin-shaped patterns; a source/drain pattern connected to the plurality of fin-shaped patterns on the field insulating layer, the source/drain pattern including bottom surfaces respectively connected to the fin-shaped patterns, and at least one connection surface connecting the bottom surfaces to each other; and a sealing insulating pattern extending along the connection surface of the source/drain pattern and an upper surface of the field insulating layer, wherein the source/drain pattern includes a silicon-germanium pattern doped with a p-type impurity.

公开(公告)号：US12021131B2

公开(公告)日：2024-06-25

申请号：US17460446

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin Jeong ,  Do Hyun Go ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US10312152B2

公开(公告)日：2019-06-04

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L27/04

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US20180355510A1

公开(公告)日：2018-12-13

申请号：US15869905

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Gyeom Kim ,  Yi Hwan Kim ,  Sun Jung Kim ,  Pan Kwi Park ,  Jeong Ho Yoo

IPC: C30B25/12 ,  C23C16/458

CPC classification number: C30B25/12 ,  C23C16/4585 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.