公开(公告)号：US11705503B2

公开(公告)日：2023-07-18

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum Kim ,  MunHyeon Kim ,  Hyoung Sub Kim ,  Tae Jin Park ,  Kwan Heum Lee ,  Chang Woo Noh ,  Maria Toledano Lu Que ,  Hong Bae Park ,  Si Hyung Lee ,  Sung Man Whang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US11010532B2

公开(公告)日：2021-05-18

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander Schmidt ,  Dong-Gwan Shin ,  Anthony Payet ,  Hyoung Soo Ko ,  Seok Hoon Kim ,  Hyun-Kwan Yu ,  Si Hyung Lee ,  In Kook Jang

IPC: G06F30/367 ,  G06F30/398 ,  H01L27/02

Abstract: A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.

公开(公告)号：US20190393347A1

公开(公告)日：2019-12-26

申请号：US16213186

申请日：2018-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG WOO KIM ,  Do Hee Kim ,  Hyo Jin Kim ,  Kang Hun Moon ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

公开(公告)号：US12040402B2

公开(公告)日：2024-07-16

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US10700203B2

公开(公告)日：2020-06-30

申请号：US16213186

申请日：2018-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Woo Kim ,  Do Hee Kim ,  Hyo Jin Kim ,  Kang Hun Moon ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L27/088

Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

公开(公告)号：US20230145260A1

公开(公告)日：2023-05-11

申请号：US17831513

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including: a plurality of fin-shaped patterns spaced apart from each other in a first direction and extending in a second direction on a substrate; a field insulating layer covering sidewalls of the plurality of fin-shaped patterns and disposed between the fin-shaped patterns; a source/drain pattern connected to the plurality of fin-shaped patterns on the field insulating layer, the source/drain pattern including bottom surfaces respectively connected to the fin-shaped patterns, and at least one connection surface connecting the bottom surfaces to each other; and a sealing insulating pattern extending along the connection surface of the source/drain pattern and an upper surface of the field insulating layer, wherein the source/drain pattern includes a silicon-germanium pattern doped with a p-type impurity.