-
公开(公告)号：US11450681B2
公开(公告)日：2022-09-20
申请号：US16844234
申请日：2020-04-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin Lee , Jongwon Kim , Shinhwan Kang , Kohji Kanamori , Jeehoon Han
IPC: H01L27/1157 , H01L27/11556 , H01L27/11521 , H01L27/11578
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
-
公开(公告)号：US09685452B2
公开(公告)日：2017-06-20
申请号：US15245218
申请日：2016-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changhyun Lee , Heonkyu Lee , Shinhwan Kang , Youngwoo Park
IPC: H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11524 , H01L27/11582 , H01L23/535
CPC classification number: H01L27/11582 , H01L23/5283 , H01L23/535 , H01L27/11524 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L27/11573
Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.
-
公开(公告)号：US09515087B2
公开(公告)日：2016-12-06
申请号：US14878453
申请日：2015-10-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yunghwan Son , Jaesung Sim , Shinhwan Kang , Youngwoo Park , Jaeduk Lee
IPC: G11C5/02 , H01L27/115 , G11C16/30 , H01L29/34 , G11C16/04
CPC classification number: H01L27/11575 , G11C5/025 , G11C16/0483 , G11C16/30 , H01L27/11517 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/34
Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及穿透 堆叠结构并连接到半导体层。
-
公开(公告)号：US12302580B2
公开(公告)日：2025-05-13
申请号：US17231600
申请日：2021-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghun Chun , Jihwan Kim , Shinhwan Kang , Jeehoon Han
IPC: H10B43/50 , H01L21/768 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
Abstract: A semiconductor memory device includes a first substrate; active or passive circuits on the first substrate; a second substrate above the active or passive circuits; gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction; channel structures penetrating through the gate electrodes and extending in the first direction, and each including a channel layer; separation regions penetrating through the gate electrodes and extending in a second direction; a through-contact plug extending through the second substrate in the first direction and electrically connecting the gate electrodes and the active or passive circuits to each other; and a barrier structure spaced apart from the through-contact plug and surrounding the through-contact plug and having first regions each having a first width, and second regions each having a second width greater than the first width.
-
5.发明公开公开(公告)号：US20240324205A1
公开(公告)日：2024-09-26
申请号：US18469705
申请日：2023-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhwan Kang , Jae-Hwang Sim
Abstract: A 3D semiconductor memory device includes a source structure, a gate stack structure disposed on the source structure and comprising insulating patterns and conductive patterns which are alternately stacked, a through-plug, a pad in contact with the through-plug, and a pad insulating pattern under the pad. The conductive patterns include a selection conductive line in contact with the through-plug. The through-plug includes an extension plug portion and a parallel plug portion. A height of the pad is less than a height of the conductive pattern.
-
Patent Agency Ranking
公开(公告)号：US11778826B2
公开(公告)日：2023-10-03
申请号：US17705513
申请日：2022-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Shinhwan Kang
IPC: H10B43/27 , H01L23/522 , H01L23/528 , H10B43/40 , H10B43/50 , H01L21/02 , H01L21/311 , H01L21/28 , H10B43/10
CPC classification number: H10B43/27 , H01L21/02532 , H01L21/02592 , H01L21/02636 , H01L21/02667 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L23/528 , H01L23/5226 , H01L29/40117 , H10B43/10 , H10B43/40 , H10B43/50
Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.
-
公开(公告)号：US20180308856A1
公开(公告)日：2018-10-25
申请号：US15832756
申请日：2017-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghan Cho , Shinhwan Kang
IPC: H01L27/11565 , H01L23/532 , H01L23/528 , H01L23/522 , H01L27/11556 , H01L27/11519 , H01L27/11582
CPC classification number: H01L27/11565 , H01L23/5226 , H01L23/5283 , H01L23/53271 , H01L27/11519 , H01L27/11556 , H01L27/11582 , H01L29/0847
Abstract: A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.
-
公开(公告)号：US09837429B2
公开(公告)日：2017-12-05
申请号：US15348009
申请日：2016-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yunghwan Son , Jaesung Sim , Shinhwan Kang , Youngwoo Park , Jaeduk Lee
IPC: H01L27/11575 , H01L27/11582 , H01L27/11573 , G11C16/30 , H01L29/34 , H01L27/11526 , G11C5/02 , G11C16/04 , H01L27/11517 , H01L27/11565 , H01L27/1157 , H01L27/11548 , H01L27/11556 , H01L27/11551
CPC classification number: H01L27/11575 , G11C5/025 , G11C16/0483 , G11C16/30 , H01L27/11517 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/34
Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
-
公开(公告)号：US12058866B2
公开(公告)日：2024-08-06
申请号：US17204248
申请日：2021-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeryong Sim , Shinhwan Kang , Jeehoon Han
CPC classification number: H10B43/50 , H01L23/481 , H10B43/27
Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.
-
公开(公告)号：US11925020B2
公开(公告)日：2024-03-05
申请号：US17473006
申请日：2021-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhwan Kang , Younghwan Son , Haemin Lee , Kohji Kanamori , Jeehoon Han
Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
-
-
-
-
-
-
-
-
-
Search Results
27
records
(took 0.016 seconds)
